公开(公告)号：US06324120B2

公开(公告)日：2001-11-27

申请号：US09779296

申请日：2001-02-08

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G11C700

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14

Abstract: A synchronous memory device and methods of operation and controlling such a device. The method of controlling the memory device includes providing block size information to the memory device, synchronously with respect to an external clock signal, wherein the block size information defines an amount of data to be output by the memory device in response to a read request. The method further includes issuing a first read request to the memory device, wherein the memory device receives the first read request synchronously with respect to a transition of the external clock signal.

Abstract translation: 一种同步存储装置及其操作和控制方法。 控制存储器件的方法包括相对于外部时钟信号向存储器件提供块大小信息，其中块大小信息定义响应于读请求而由存储器件输出的数据量。 该方法还包括向存储器件发出第一读取请求，其中存储器件相对于外部时钟信号的转换同步地接收第一读取请求。

公开(公告)号：US6085284A

公开(公告)日：2000-07-04

申请号：US252993

申请日：1999-02-19

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G06F13/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: A method of operating a synchronous memory device, wherein the memory device includes a plurality of memory cells and a register for storing an identification value which identifies the memory device on a bus. Block size information is provided to the memory device, wherein the block size information specifies an amount of data to be output onto a bus in response to a read request. The read request is issued to the memory device, and includes identification information, wherein in response to the read request, the memory device determines whether the identification information corresponds to the identification value stored in the register. When the identification information corresponds to the identification value, the memory device outputs an amount of data corresponding to the block size information onto the bus synchronously with respect to at least a first external clock. The memory device may further include a programmable register. An access time value may be provided to the memory device wherein, in response, the memory device stores the access time value in the programmable register. Here, the access time value is representative of a delay to transpire before data is output onto the bus in response to the read request.

Abstract translation: 一种操作同步存储器件的方法，其中所述存储器件包括多个存储器单元和用于存储识别总线上的存储器件的标识值的寄存器。 块大小信息被提供给存储器件，其中块大小信息响应于读请求指定要输出到总线上的数据量。 读取请求被发送到存储器件，并且包括识别信息，其中响应于读取请求，存储器件确定识别信息是否对应于存储在寄存器中的识别值。 当识别信息对应于识别值时，存储器件相对于至少第一外部时钟同步地将相应于块大小信息的数据量输出到总线上。 存储器件还可以包括可编程寄存器。 访问时间值可以被提供给存储器件，其中作为响应，存储器件将访问时间值存储在可编程寄存器中。 这里，访问时间值表示响应于读取请求而将数据输出到总线之前的延迟。

公开(公告)号：US6067592A

公开(公告)日：2000-05-23

申请号：US357989

申请日：1999-07-21

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: A system for use in a computer, the system comprises a memory device and a controller or master to generate a request to provide data. The memory device includes at least one section of memory, having a plurality of memory cells, and a programmable register to store a value which is representative of a number of clock cycles of a first external clock signal to transpire before the memory device outputs data onto the bus in response to the request to provide data. The memory device may further include a plurality of output drivers and a delay lock loop circuitry wherein the delay lock loop circuitry generates a first internal clock signal using the first external clock signal. The plurality of output drivers, in response to the first internal clock signal, output data onto the bus. The plurality of output drivers output data on the bus after the number of clock cycles of the first external clock signal transpire and synchronously with respect to the first external clock signal. The delay lock loop circuitry may also generate the first internal clock signal using the first external clock signal and a second external clock signal.

Abstract translation: 一种在计算机中使用的系统，该系统包括存储器装置和控制器或主机，以产生提供数据的请求。 存储器件包括具有多个存储器单元的存储器的至少一个部分，以及可编程寄存器，用于存储表示在存储器件将数据输出到第一外部时钟信号之前要发出的第一外部时钟信号的时钟周期数的值 总线响应请求提供数据。 存储器件还可以包括多个输出驱动器和延迟锁定环路，其中延迟锁定环电路使用第一外部时钟信号产生第一内部时钟信号。 多个输出驱动器响应于第一内部时钟信号将数据输出到总线上。 多个输出驱动器在第一外部时钟信号的时钟周期数量相对于第一外部时钟信号发生并同步地在总线上输出数据。 延迟锁定环电路还可以使用第一外部时钟信号和第二外部时钟信号产生第一内部时钟信号。

公开(公告)号：US5841715A

公开(公告)日：1998-11-24

申请号：US796782

申请日：1997-02-10

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G11C7/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Abstract translation: 本发明包括一个包括至少两个半导体器件的存储器子系统，包括连接到总线的至少一个存储器件，其中总线包括用于承载所有存储器件所需的所有地址，数据和控制信息的多条总线 ，其中控制信息包括设备选择信息，并且总线具有比单个地址中的位数少得多的总线，并且总线承载设备选择信息，而不需要直接连接到各个设备的单独的设备选择线 。 本发明还包括用于主设备和从设备在总线上通信的协议，以及用于每个设备中的寄存器以区分每个设备并允许总线请求被引导到单个或所有设备的协议。 本发明包括对现有技术设备的修改，以允许它们实现本发明的新特征。 在一个优选实施方式中，8个总线数据线和一个AddressValid总线携带地址，数据和控制信息，用于高达40位宽的存储器地址。

公开(公告)号：US5513327A

公开(公告)日：1996-04-30

申请号：US222646

申请日：1994-03-31

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G06F13/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: A dynamic random access memory (DRAM). The DRAM comprises a first circuit for providing a clock signal and a conductor for coupling the DRAM to a bus. A receiver circuit is coupled to the conductor and the first circuit for latching information received from the conductor in response to detecting each of a rising edge of the clock signal and a falling edge of the clock signal. The receiver circuit may include a first input receiver for latching information in response to the rising edge of the clock signal and a second input receiver for latching information in response to the falling edge of the clock signal.

Abstract translation: 动态随机存取存储器（DRAM）。 DRAM包括用于提供时钟信号的第一电路和用于将DRAM耦合到总线的导体。 响应于检测到时钟信号的上升沿和时钟信号的下降沿，接收器电路耦合到导体和第一电路，用于锁存从导体接收的信息。 接收器电路可以包括用于响应于时钟信号的上升沿来锁存信息的第一输入接收器和用于响应于时钟信号的下降沿来锁存信息的第二输入接收器。

公开(公告)号：US5319755A

公开(公告)日：1994-06-07

申请号：US954945

申请日：1992-09-30

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G06F13/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: An apparatus for storing and retrieving data is described. The apparatus includes a circuitry for initiating data transmission, a first memory, a second memory, and a multiline bus for transferring control information, addresses, and the data. The control information includes information for selecting one of the first and second memories without using any separate memory select line. Configuration circuitry is provided for assigning a first identification value to the first memory and a second identification value to the second memory. The configuration circuitry includes a first reset line for coupling the circuitry for initiating data transmission to the first memory, a second reset line for coupling the first memory to the second memory, a first identification register for the first memory, a second identification register for the second memory, circuitry for generating a first reset signal and a second reset signal and for sending the first and second reset signals to the first identification register, circuitry for propagating the first and second reset signals from the first identification register to the second identification register, circuitry for resetting the first and second identification registers in response to the first reset signal, and circuitry for setting the first identification register to the first identification value and the second identification register to the second identification value in response to the second reset signal.

Abstract translation: 描述了一种用于存储和检索数据的装置。 该装置包括用于发起数据传输的电路，第一存储器，第二存储器和用于传送控制信息，地址和数据的多线总线。 控制信息包括用于在不使用任何单独的存储器选择线的情况下选择第一和第二存储器之一的信息。 提供配置电路用于将第一标识值分配给第一存储器，并将第二标识值分配给第二存储器。 配置电路包括用于将用于启动数据传输的电路耦合到第一存储器的第一复位线，用于将第一存储器耦合到第二存储器的第二复位线，用于第一存储器的第一识别寄存器， 第二存储器，用于产生第一复位信号和第二复位信号以及用于将第一和第二复位信号发送到第一识别寄存器的电路，用于将第一和第二复位信号从第一识别寄存器传播到第二识别寄存器的电路， 用于响应于第一复位信号复位第一和第二识别寄存器的电路，以及用于响应于第二复位信号将第一识别寄存器设置为第一识别值和第二识别寄存器到第二识别值的电路。

公开(公告)号：US08185853B2

公开(公告)日：2012-05-22

申请号：US12594873

申请日：2008-02-28

Applicant: Jaeha Kim ,  Kevin D. Jones ,  Mark Horowitz

Inventor： Jaeha Kim ,  Kevin D. Jones ,  Mark Horowitz

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: Embodiments in the present disclosure pertain to domain translators. A domain translator converts a variable from one domain to a different domain. Domains include, but are not limited to, voltage, current, frequency, phase, delay, and duty-cycle. In particular, domain translators enable conversion between standard voltage and current domains commonly used by circuit simulators to other domains such as frequency, phase, delay, duty-cycle, etc., so that linear analysis can be performed on a wide range of circuits that exhibit linear behavior in domains other than voltage and current.

Abstract translation: 本公开的实施例涉及域翻译器。 域转换器将变量从一个域转换为不同的域。 域包括但不限于电压，电流，频率，相位，延迟和占空比。 特别地，域转换器使得电路模拟器通常使用的标准电压和电流域之间能够转换到诸如频率，相位，延迟，占空比等其他领域，使得可以在宽范围的电路上执行线性分析， 在电压和电流以外的领域表现出线性行为。

公开(公告)号：US08116366B2

公开(公告)日：2012-02-14

申请号：US12149157

申请日：2008-04-28

Applicant: Toshitsugu Kawashima ,  Mark Horowitz

Inventor： Toshitsugu Kawashima ,  Mark Horowitz

IPC: H03H7/30 ,  H03K5/159

CPC classification number: H04L25/03057 ,  H04L25/03235

Abstract: Disclosed is a delayed decision feedback sequence estimator comprising a delayed decision feedback sequence estimator main unit including DDFSE computing unit group including (L+M) DDFSE computing units, equal in number to a length of each of plurality of blocks into which a received data symbol sequence is divided; wherein (L+M) DDFSE computing units are connected in a pipeline configuration to execute delayed decision feedback sequence estimation of the blocks in parallel; and an edge effect detection and correction circuit that detects an edge effect due to processing the delayed decision feedback sequence estimation of the separated block and corrects a relevant bit error.

Abstract translation: 公开了一种延迟判定反馈序列估计器，其包括延迟判定反馈序列估计器主单元，该延迟判定反馈序列估计器主单元包括DDFSE计算单元组，其包括（L + M）DDFSE计算单元，其数量等于多个块中的每一个的长度，其中接收的数据符号 序列分为 其中（L + M）DDFSE计算单元以流水线配置连接以并行地执行块的延迟判定反馈序列估计; 以及边缘效应检测和校正电路，其检测由于处理分离块的延迟的判定反馈序列估计的边缘效应并校正相关的位错误。

公开(公告)号：US08027531B2

公开(公告)日：2011-09-27

申请号：US11187699

申请日：2005-07-21

Applicant: Bennett Wilburn ,  Neel Joshi ,  Marc C. Levoy ,  Mark Horowitz

Inventor： Bennett Wilburn ,  Neel Joshi ,  Marc C. Levoy ,  Mark Horowitz

IPC: G06K9/00 ,  G06K7/00 ,  G06T15/00 ,  H04N13/02 ,  H04N13/04

CPC classification number: H04N5/247 ,  H04N5/3532 ,  H04N5/357

Abstract: This invention relates to an apparatus and a method for video capture of a three-dimensional region of interest in a scene using an array of video cameras. The video cameras of the array are positioned for viewing the three-dimensional region of interest in the scene from their respective viewpoints. A triggering mechanism is provided for staggering the capture of a set of frames by the video cameras of the array. The apparatus has a processing unit for combining and operating on the set of frames captured by the array of cameras to generate a new visual output, such as high-speed video or spatio-temporal structure and motion models, that has a synthetic viewpoint of the three-dimensional region of interest. The processing involves spatio-temporal interpolation for determining the synthetic viewpoint space-time trajectory. In some embodiments, the apparatus computes a multibaseline spatio-temporal optical flow.

Abstract translation: 本发明涉及使用摄像机阵列在场景中对三维感兴趣区域进行视频采集的装置和方法。 阵列的摄像机被定位成从它们各自的视点观看场景中的感兴趣的三维区域。 提供了一种触发机制，用于通过阵列的摄像机交错捕获一组帧。 该装置具有处理单元，用于组合并操作由相机阵列捕获的一组帧，以产生新的视觉输出，例如高速视频或时空结构和运动模型，其具有合成视点 感兴趣的三维区域。 该处理涉及用于确定合成视点时空轨迹的时空插值。 在一些实施例中，该装置计算多基线时空光流。

公开(公告)号：US07859436B2

公开(公告)日：2010-12-28

申请号：US12258285

申请日：2008-10-24

Applicant: Carl Werner ,  Mark Horowitz ,  Pak Chau ,  Scott Best ,  Stefanos Sidiropoulos

Inventor： Carl Werner ,  Mark Horowitz ,  Pak Chau ,  Scott Best ,  Stefanos Sidiropoulos

IPC: H03M7/00

CPC classification number: H04L25/4917 ,  G06F13/1678 ,  G06F13/4068 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C8/10 ,  G11C11/56 ,  G11C27/02 ,  G11C2207/108 ,  H04L7/0331 ,  H04L7/0332 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0296 ,  H04L25/0298 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/08 ,  H04L25/4902

Abstract: A memory device includes a receiver to receive a first input data signal and to create an output signal corresponding to the first input data signal and a voltage representative of a second signal received earlier in time than the first input data signal. A memory system includes a memory controller and one or more memory devices, at least one or which includes a receiver to receive a first input data signal and to create an output signal corresponding to the first input data signal and a voltage representative of a second signal received earlier in time than the first input data signal.

Abstract translation: 存储器件包括接收器，用于接收第一输入数据信号并产生对应于第一输入数据信号的输出信号和代表在时间上比第一输入数据信号更早接收的第二信号的电压。 存储器系统包括存储器控制器和一个或多个存储器设备，至少一个存储器设备或包括接收器以接收第一输入数据信号并产生对应于第一输入数据信号的输出信号和表示第二信号的电压 比第一输入数据信号更早地接收。