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    HYBRID MEMORY MODULE AND SYSTEM AND METHOD OF OPERATING THE SAME
    82.
    发明申请
    HYBRID MEMORY MODULE AND SYSTEM AND METHOD OF OPERATING THE SAME 审中-公开
    混合存储器模块及其操作方法

    公开(公告)号：US20150169238A1

    公开(公告)日：2015-06-18

    申请号：US14536588

    申请日：2014-11-07

    申请人： Netlist, Inc.

    发明人： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

    IPC分类号： G06F3/06

    CPC分类号： G06F12/0871 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0897 ,  G06F13/28 ,  G06F2206/1014 ,  G06F2212/214 ,  G06F2212/313 ,  G06F2212/7201 ,  G06F2212/7208

    摘要： A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

    摘要翻译： 存储器模块包括被配置为耦合到计算机系统中的存储器通道并且能够用作计算机系统的主存储器的非易失性存储器子系统，为计算机系统提供存储的非易失性存储器子系统，以及耦合到 易失性存储器子系统，非易失性存储器子系统和C / A总线。 模块控制器被配置为控制易失性存储器子系统和非易失性存储器子系统之间的模块内数据传输。 模块控制器还被配置为监视C / A总线上的C / A信号，并根据C / A信号调度模块内数据传输，使得模块内数据传输不与对易失性的访问冲突 内存子系统由内存控制器。

    Module having at least one thermally conductive layer between printed circuit boards
    83.
    发明授权
    Module having at least one thermally conductive layer between printed circuit boards 有权
    模块在印刷电路板之间具有至少一个导热层

    公开(公告)号：US08971045B1

    公开(公告)日：2015-03-03

    申请号：US13731014

    申请日：2012-12-30

    申请人： NETLIST, Inc.

    发明人： Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

    IPC分类号： H05K7/20 ,  H05K1/02

    CPC分类号： H05K1/0203 ,  H05K1/144 ,  H05K2201/10189 ,  H05K2201/1056 ,  H05K2201/2018 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/4913

    摘要： A module is electrically connectable to a computer system. The module includes an edge connector with a plurality of electrical contacts electrically connectable to the computer system, at least one layer of thermally conductive material thermally coupled to the edge connector, and first and second printed circuit boards each having a plurality of integrated circuit components that are electrically coupled to the edge connector and thermally coupled to the at least one layer of thermally conductive material. The at least one layer of thermally conductive material are disposed between the first and second printed circuit boards.

    摘要翻译： 模块可电连接到计算机系统。 模块包括边缘连接器，其具有可电连接到计算机系统的多个电触点，热耦合到边缘连接器的至少一层导热材料，以及第一和第二印刷电路板，每个具有多个集成电路部件， 电耦合到边缘连接器并且热耦合到至少一个导热材料层。 至少一层导热材料设置在第一和第二印刷电路板之间。

    Isolation Switching For Backup Of Registered Memory
    86.
    发明申请
    Isolation Switching For Backup Of Registered Memory 有权
    用于备份注册内存的隔离切换

    公开(公告)号：US20140156920A1

    公开(公告)日：2014-06-05

    申请号：US14173242

    申请日：2014-02-05

    申请人： Netlist, Inc.

    发明人： Chi-She Chen ,  Jeffrey C. Solomon ,  Scott H. Milton ,  Jayesh Bhakta

    IPC分类号： G06F12/02

    CPC分类号： G06F3/061 ,  G06F3/0634 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/1072 ,  G06F11/1441 ,  G06F11/2015 ,  G06F12/00 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C5/141 ,  G11C5/143 ,  G11C7/1072 ,  G11C11/005 ,  G11C14/0018 ,  G11C29/52

    摘要： Certain embodiments described herein include a memory system having a register coupled to a host system and operable to receive address and control signals from the host system, a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the register, the volatile memory subsystem, and the controller. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the register to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the non-volatile memory subsystem using the controller, and is operable to selectively isolate the volatile memory subsystem from the register.

    摘要翻译： 本文描述的某些实施例包括存储器系统，其具有耦合到主机系统并且可操作以从主机系统接收地址和控制信号的寄存器，易失性存储器子系统，非易失性存储器子系统，耦合到非易失性存储器 子系统和耦合到寄存器，易失性存储器子系统和控制器的电路。 在第一操作模式中，电路可操作以选择性地将控制器与易失性存储器子系统隔离，并且将易失性存储器子系统选择性地耦合到寄存器以允许在易失性存储器子系统和主机系统之间传送数据。 在第二操作模式中，电路可操作以选择性地将控制器耦合到易失性存储器子系统，以允许使用控制器在易失性存储器子系统和非易失性存储器子系统之间传送数据，并且可操作地将 来自寄存器的易失性存储器子系统。

    Apparatus and method for self-test in a multi-rank memory module
    87.
    发明授权
    Apparatus and method for self-test in a multi-rank memory module 有权
    用于多级存储器模块中的自检的装置和方法

    公开(公告)号：US08689064B1

    公开(公告)日：2014-04-01

    申请号：US13745790

    申请日：2013-01-19

    申请人： Netlist, Inc.

    发明人： Hyun Lee ,  Jayesh R. Bhakta ,  Soonju Choi

    IPC分类号： G11C29/00

    CPC分类号： G11C29/12 ,  G11C5/04

    摘要： A memory module for operating with a system memory controller comprises a plurality of data ports, a plurality of memory devices organized in ranks, and a plurality of data handlers. Each respective data handler is coupled to a respective set of data ports of the plurality of data ports and to a respective set of memory devices of the plurality of memory devices. Each set of memory devices include at least one memory device from each rank. In a normal mode, each respective data handler is configured to provide write data received from the system memory controller via the respective data ports to the respective set of memory devices. In a test mode, each respective data handler is configured to provide test data generated in the respective data handler to the respective set of memory devices.

    摘要翻译： 用于与系统存储器控制器一起操作的存储器模块包括多个数据端口，以等级排列的多个存储器件以及多个数据处理器。 每个相应的数据处理器被耦合到多个数据端口中的相应的一组数据端口和多个存储器件的相应的一组存储器件。 每组存储器件包括来自每个等级的至少一个存储器件。 在正常模式中，每个相应的数据处理器被配置为将从系统存储器控制器接收的写入数据经由相应的数据端口提供给相应的存储器组。 在测试模式中，每个相应的数据处理器被配置为将相应数据处理器中生成的测试数据提供给相应的存储器设备组。

    MEMORY MODULE HAVING OPEN-DRAIN OUTPUT FOR ERROR REPORTING AND FOR INITIALIZATION
    88.
    发明申请
    MEMORY MODULE HAVING OPEN-DRAIN OUTPUT FOR ERROR REPORTING AND FOR INITIALIZATION 有权

    公开(公告)号：US20220382693A1

    公开(公告)日：2022-12-01

    申请号：US17840593

    申请日：2022-06-14

    申请人： Netlist, Inc.

    发明人： Hyun Lee

    IPC分类号： G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G06F9/445 ,  G06F13/24 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G06F12/06

    摘要： According to certain aspects, a memory subsystem is coupled to a memory controller of a host computer system via an interface. The memory subsystem comprises dynamic random access memory elements and a memory subsystem controller. During a normal memory read or write operation, the memory subsystem controller is configured to receive address and command signals associated with the memory read or write operations and to control the dynamic random access memory elements in accordance with the address and command signals. The memory subsystem controller is further configured to output via the open drain output a parity error signal in response to a parity error having occurred during the memory read or write operation. During an initialization operation, the memory subsystem controller is configured to output via the open train output a signal related to one or more parts of initialization operation sequences.

    Memory module with local synchronization and method of operation
    89.
    发明授权
    Memory module with local synchronization and method of operation 有权

    公开(公告)号：US11513955B2

    公开(公告)日：2022-11-29

    申请号：US17141978

    申请日：2021-01-05

    申请人： NETLIST, INC.

    发明人： Hyun Lee ,  Jayesh R. Bhakta

    IPC分类号： G06F12/0802 ,  G11C5/04 ,  G11C29/02 ,  G11C7/10

    摘要： A memory module is operable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals and a system clock from the memory controller and to output a module clock, module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in one or more ranks, while the data buffer control signals, together with the module clock, are provided to a plurality of buffer circuits corresponding to respective groups of memory devices and are used to control data paths in the buffer circuits. The plurality of buffer circuits include clock regeneration circuits to regenerate clock signals with programmable delays from the module clock. The regenerated clock signals are provided to respective groups of memory devices so as to locally sync the buffer circuits with respective groups of memory devices.

    Computer memory expansion device and method of operation
    90.
    发明授权
    Computer memory expansion device and method of operation 有权

    公开(公告)号：US11500797B2

    公开(公告)日：2022-11-15

    申请号：US17336262

    申请日：2021-06-01

    申请人： Netlist Inc.

    发明人： Jordan Horwich ,  Jerry Alston ,  Chih-Cheh Chen ,  Patrick Lee ,  Scott Milton ,  Jeekyoung Park

    IPC分类号： G06F13/16 ,  G06F12/0862 ,  G06F12/0891

    摘要： A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.