公开(公告)号：US20130246824A1

公开(公告)日：2013-09-19

申请号：US13891747

申请日：2013-05-10

Applicant: Martin G. Dixon ,  Scott D. Rodgers ,  Taraneh Bahrami ,  Stephen H. Gunther ,  Prashant Sethi ,  Per Hammarlund

Inventor： Martin G. Dixon ,  Scott D. Rodgers ,  Taraneh Bahrami ,  Stephen H. Gunther ,  Prashant Sethi ,  Per Hammarlund

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3293 ,  G06F9/30083 ,  G06F9/3009 ,  Y02D10/122 ,  Y02D50/20

Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有解码逻辑的核的处理器，用于解码指定要监视的位置的标识的指令和定时器值，以及耦合到解码逻辑的定时器，以执行相对于 定时器值。 处理器还可以包括耦合到核的功率管理单元，以至少部分地基于定时器值来确定低功率状态的类型，并且使处理器响应于该确定而进入低功率状态。 描述和要求保护其他实施例。

公开(公告)号：US20130219399A1

公开(公告)日：2013-08-22

申请号：US13843164

申请日：2013-03-15

Applicant: Hong Wang ,  John Shen ,  Edward Grochowski ,  Richard Hankins ,  Gautham Chinya ,  Bryant Bigbee ,  Shivnandan Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju Patel ,  James Held

Inventor： Hong Wang ,  John Shen ,  Edward Grochowski ,  Richard Hankins ,  Gautham Chinya ,  Bryant Bigbee ,  Shivnandan Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju Patel ,  James Held

IPC: G06F9/48

CPC classification number: G06F9/3867 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/4843 ,  G06F9/4881

Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Abstract translation: 在一个实施例中，提供了一种方法。 该方法包括响应于在应用级程序的控制下对第二指令定序器执行用户级指令来管理第一指令定序器上的用户级线程。 在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。 第一用户级指令至少具有1）引用一个或多个指令定序器的字段，或者2）使用指向代码执行代码时特定寻址一个或多个指令定序器的代码的指针进行隐式引用。

公开(公告)号：US20130219096A1

公开(公告)日：2013-08-22

申请号：US13844343

申请日：2013-03-15

Applicant: HONG WANG ,  PER HAMMARLUND ,  XIANG ZOU ,  JOHN P. SHEN ,  XINMIN TIAN ,  MILIND GIRKAR ,  PERRY H. WANG ,  PIYUSH N. DESAI

Inventor： HONG WANG ,  PER HAMMARLUND ,  XIANG ZOU ,  JOHN P. SHEN ,  XINMIN TIAN ,  MILIND GIRKAR ,  PERRY H. WANG ,  PIYUSH N. DESAI

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/4843 ,  G06F11/3024 ,  G06F11/348 ,  G06F12/0875 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/452

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Abstract translation: 用于可激活其他线程的可编程事件驱动产量机制的方法，装置和程序装置。 在一个实施例中，一种装置包括执行多个指令的执行资源和用于检测指示低水平进展的状况的监视器。 响应于检测到指示低水平进展的状况，监视器可以通过传送到处理程序来中断程序的处理。 在另一个实施例中，线程切换逻辑可以耦合到监视多线程执行逻辑内的事件的多个事件监视器。 线程开关逻辑至少部分地基于一个或多个性能监视器的可编程状态来切换线程。

公开(公告)号：US20130205122A1

公开(公告)日：2013-08-08

申请号：US13791298

申请日：2013-03-08

Applicant: Hong WANG ,  John SHEN ,  Hong JIANG ,  Richard HANKINS ,  Per HAMMARLUND ,  Dion RODGERS ,  Gautham CHINYA ,  Baiju PATEL ,  Shiv KAUSHIK ,  Bryant BIGBEE ,  Gad SHEAFFER ,  Yoav Talgam ,  Yuval YOSEF ,  James P. HELD

Inventor： Hong WANG ,  John SHEN ,  Hong JIANG ,  Richard HANKINS ,  Per HAMMARLUND ,  Dion RODGERS ,  Gautham CHINYA ,  Baiju PATEL ,  Shiv KAUSHIK ,  Bryant BIGBEE ,  Gad SHEAFFER ,  Yoav Talgam ,  Yuval YOSEF ,  James P. HELD

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06T1/20

Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在加速器和与其耦合的指令定序器之间直接通信的方法，其中加速器相对于指令定序器是异质资源。 可以使用接口来提供这些资源之间的通信。 通过这种通信机制，用户级应用可以直接与加速器进行通信，而无需操作系统支持。 此外，指令定序器和加速器可以并行地执行操作。 描述和要求保护其他实施例。

公开(公告)号：US20130073835A1

公开(公告)日：2013-03-21

申请号：US13675910

申请日：2012-11-13

Applicant: Quinn A. Jacobson ,  Hong Wang ,  John P. Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik

Inventor： Quinn A. Jacobson ,  Hong Wang ,  John P. Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik

IPC: G06F9/30

CPC classification number: G06F9/526 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

Abstract: A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

Abstract translation: 处理器可以包括地址监视表和原子更新表以支持推测性线程。 处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。 处理器可以支持以下一个或多个原语：写入状态寄存器的指令，触发提交缓冲存储器更新的指令，读取状态状态寄存器的指令和/或 指令清除与陷阱/异常/中断处理相关联的状态位之一。 还描述和要求保护其他实施例。

公开(公告)号：US20130054940A1

公开(公告)日：2013-02-28

申请号：US13608970

申请日：2012-09-10

Applicant: Hong Wang ,  John Shen ,  Ed Grochowski ,  James Paul Held ,  Bryant Bigbee ,  Shivnandan D. Kaushik ,  Gautham Chinya ,  Xiang Zou ,  Per Hammarlund ,  Xinmin Tian ,  Anil Aggarwal ,  Scott Dion Rodgers ,  Prashant Sethi ,  Baiju V. Patel ,  Richard Andrew Hankins

Inventor： Hong Wang ,  John Shen ,  Ed Grochowski ,  James Paul Held ,  Bryant Bigbee ,  Shivnandan D. Kaushik ,  Gautham Chinya ,  Xiang Zou ,  Per Hammarlund ,  Xinmin Tian ,  Anil Aggarwal ,  Scott Dion Rodgers ,  Prashant Sethi ,  Baiju V. Patel ,  Richard Andrew Hankins

IPC: G06F9/312

CPC classification number: G06F9/3867 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/4843 ,  G06F9/4881

Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Abstract translation: 在一个实施例中，提供了一种方法。 该方法包括响应于在应用级程序的控制下对第二指令定序器执行用户级指令来管理第一指令定序器上的用户级线程。 在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。 第一用户级指令至少具有1）引用一个或多个指令定序器的字段，或者2）使用指向代码执行代码时特定寻址一个或多个指令定序器的代码的指针进行隐式引用。

公开(公告)号：US08332619B2

公开(公告)日：2012-12-11

申请号：US13314826

申请日：2011-12-08

Applicant: Quinn A. Jacobson ,  Hong Wang ,  John P. Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant Bigbee ,  Shivnandan D. Kaushik

Inventor： Quinn A. Jacobson ,  Hong Wang ,  John P. Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant Bigbee ,  Shivnandan D. Kaushik

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC classification number: G06F9/526 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

Abstract: A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

Abstract translation: 处理器可以包括地址监视表和原子更新表以支持推测性线程。 处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。 处理器可以支持以下一个或多个原语：写入状态寄存器的指令，触发提交缓冲存储器更新的指令，读取状态状态寄存器的指令和/或 指令清除与陷阱/异常/中断处理相关联的状态位之一。 还描述和要求保护其他实施例。

公开(公告)号：US20120192000A1

公开(公告)日：2012-07-26

申请号：US13436835

申请日：2012-03-30

Applicant: Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

Inventor： Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

IPC: G06F1/00

CPC classification number: G06F1/3287 ,  G06F1/3209 ,  Y02D10/171

Abstract: A low cost, low power consumption scalable architecture is provided to allow a computer system to be managed remotely during all system power states. In a lowest power state, power is only applied to minimum logic necessary to examine a network packet. Power is applied for a short period of time to an execution subsystem and one of a plurality of cores selected to handle processing of received service requests. After processing the received service requests, the computer system returns to the lowest power state.

Abstract translation: 提供了低成本，低功耗的可扩展架构，以允许在所有系统电源状态期间远程管理计算机系统。 在最低功率状态下，功率仅适用于检查网络分组所需的最小逻辑。 将电力短时间施加到执行子系统，并且被选择用于处理所接收的服务请求的处理的多个核心中的一个。 在处理接收到的服务请求之后，计算机系统返回到最低功率状态。

公开(公告)号：US08019947B2

公开(公告)日：2011-09-13

申请号：US11254286

申请日：2005-10-19

Applicant: Quinn A. Jacobson ,  Hong Wang ,  John Shen ,  Per Hammarlund

Inventor： Quinn A. Jacobson ,  Hong Wang ,  John Shen ,  Per Hammarlund

IPC: G06F12/00

CPC classification number: G06F9/542 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F12/0831 ,  G06F2209/543

Abstract: A technique for thread synchronization and communication. More particularly, embodiments of the invention pertain to managing communication and synchronization among two or more threads of instructions being executing by one or more microprocessors or microprocessor cores.

Abstract translation: 一种用于线程同步和通信的技术。 更具体地，本发明的实施例涉及管理由一个或多个微处理器或微处理器核执行的两个或多个指令线程之间的通信和同步。

公开(公告)号：US20110154079A1

公开(公告)日：2011-06-23

申请号：US12641534

申请日：2009-12-18

Applicant: Martin G. Dixon ,  Scott D. Rodgers ,  Taraneh Bahrami ,  Stephen H. Gunther ,  Prashant Sethi ,  Per Hammarlund

Inventor： Martin G. Dixon ,  Scott D. Rodgers ,  Taraneh Bahrami ,  Stephen H. Gunther ,  Prashant Sethi ,  Per Hammarlund

IPC: G06F1/32 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3293 ,  G06F9/30083 ,  G06F9/3009 ,  Y02D10/122 ,  Y02D50/20

Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有解码逻辑的核的处理器，用于解码指定要监视的位置的标识的指令和定时器值，以及耦合到解码逻辑的定时器，以执行相对于 定时器值。 处理器还可以包括耦合到核的功率管理单元，以至少部分地基于定时器值来确定低功率状态的类型，并且使处理器响应于该确定而进入低功率状态。 描述和要求保护其他实施例。