公开(公告)号：US20170255591A1

公开(公告)日：2017-09-07

申请号：US15600006

申请日：2017-05-19

Applicant: STMicroelectronics SA

Inventor： Philippe Escalona

IPC: G06F15/76 ,  G06F21/75 ,  G06F9/30 ,  G06F21/00

CPC classification number: G06F15/76 ,  G06F9/30156 ,  G06F21/00 ,  G06F21/75

Abstract: A method for securing a data processing system having a processing unit is disclosed. At least a group of N1 digital words of m1 bits is selected from among the set of M1 digital words. N1 is less than M1. These words are selected in such a way that each selected digital word differs from all the other selected digital words by a number of bits at least equal to an integer p which is at least equal to 2. The group of N1 digital words of m1 bits forms at least one group of N1 executable digital instructions. The processing unit is configured to make it capable of executing each instruction of the at least one group of N1 executable digital instructions.

公开(公告)号：US09755610B2

公开(公告)日：2017-09-05

申请号：US14981189

申请日：2015-12-28

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Frederic Gianesello ,  Romain Pilard ,  Cedric Durand

IPC: H01F27/28 ,  H01F5/00 ,  H01F21/02 ,  H01F21/12 ,  H01F7/06 ,  H04B1/40 ,  H03H7/42 ,  H01F27/38 ,  H01L23/522 ,  H01F27/29 ,  H01F27/40 ,  H04W88/02

CPC classification number: H03H7/42 ,  H01F27/2804 ,  H01F27/29 ,  H01F27/38 ,  H01F27/40 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2924/0002 ,  H04W88/02 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit.

公开(公告)号：US09735772B2

公开(公告)日：2017-08-15

申请号：US14865618

申请日：2015-09-25

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Alexandre Dray ,  Emmanuel Josse

IPC: H01L25/00 ,  H03K17/687 ,  H01L21/66 ,  G01R31/28 ,  H01L27/02

CPC classification number: H03K17/687 ,  G01R31/2884 ,  H01L22/22 ,  H01L22/34 ,  H01L27/0207

Abstract: An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.

公开(公告)号：US20170192170A1

公开(公告)日：2017-07-06

申请号：US14984563

申请日：2015-12-30

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Charles BAUDOT ,  Alain CHANTRE ,  Sébastien CREMER

IPC: G02B6/122 ,  G02B6/42 ,  G02B6/34 ,  G02B6/136 ,  G02B6/132

CPC classification number: G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  G02B6/34 ,  G02B6/4201 ,  G02B6/4214 ,  G02B2006/12147

Abstract: A method is for making a photonic chip including EO devices having multiple thicknesses. The method may include forming a first semiconductor layer over a semiconductor film, forming a second semiconductor layer over the first semiconductor layer, and forming a mask layer over the second semiconductor layer. The method may include performing a first selective etching of the mask layer to provide initial alignment trenches, performing a second etching, aligned with some of the initial alignment trenches and using the first semiconductor layer as an etch stop, to provide multi-level trenches, and filling the multi-level trenches to make the EO devices having multiple thicknesses.

公开(公告)号：US20170186623A1

公开(公告)日：2017-06-29

申请号：US15390077

申请日：2016-12-23

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Nicolas POSSEME ,  Maxime Garcia-Barros ,  Yves Morand

IPC: H01L21/324 ,  H01L21/322 ,  H01L29/78 ,  H01L21/02 ,  H01L21/447 ,  H01L21/762 ,  H01L21/223

CPC classification number: H01L21/324 ,  H01L21/02057 ,  H01L21/223 ,  H01L21/2236 ,  H01L21/31155 ,  H01L21/3221 ,  H01L21/447 ,  H01L21/762 ,  H01L21/823468 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7827

Abstract: There is provided a method for manufacturing a transistor from a stack including at least one gate pattern comprising at least one flank, the method including forming at least one gate spacer over at least the flank of the gate pattern; and reducing, after a step of exposure of the stack to a temperature greater than or equal to 600° C., of a dielectric permittivity of the at least one gate spacer, the reducing including at least one ion implantation in a portion at least of a thickness of the at least one gate spacer.

公开(公告)号：US20170179250A1

公开(公告)日：2017-06-22

申请号：US14973825

申请日：2015-12-18

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Caubet ,  Florian Domengie ,  Carlos Augusto Suarez Segovia ,  Aurelie Bajolet ,  Onintza Ros Bengoechea

IPC: H01L29/49 ,  H01L29/40

CPC classification number: H01L21/28088 ,  H01L29/4966

Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.

公开(公告)号：US20170177980A1

公开(公告)日：2017-06-22

申请号：US15381919

申请日：2016-12-16

Applicant: STMicroelectronics SA

Inventor： Manu ALIBAY ,  Stéphane AUBERGER ,  Bogdan-Florin STANCIULESCU

IPC: G06K9/62 ,  H04N5/232

CPC classification number: G06K9/6289 ,  G06K9/46 ,  G06K2009/4666 ,  G06T7/246 ,  G06T2207/10016 ,  G06T2207/30244 ,  H04N5/23238 ,  H04N5/23254 ,  H04N5/23258 ,  H04N5/23267 ,  H04N5/2329

Abstract: A method generates a binary descriptor associated with a given point in a current frame of a succession of video frames obtained by an apparatus such as an image sensor. The method includes determining a pattern of points pairs around said given point in the current frame, and performing intensity comparison processing between the two points of each pair. The apparatus is likely to move in a rotation between the previous frame and the current frame. The method includes processing the pattern of points of the current frame with tridimensional rotation information representative of the apparatus rotation between the previous frame and the current frame and obtained from inertial measurements provided by at least one inertial sensor.

公开(公告)号：US20170146578A1

公开(公告)日：2017-05-25

申请号：US15139801

申请日：2016-04-27

Applicant: STMICROELECTRONICS SA

Inventor： Marc HOUDEBINE ,  Sebastien Dedieu

IPC: G01R23/10

CPC classification number: G01R23/10 ,  G01R23/02 ,  H03D13/001

Abstract: A method includes a) counting whole periods of a signal during a first period of a reference signal, b) repeating step a) for each period of the reference signal until a first duration is equal to a first quantity of periods of the reference signal, and c) determining a first average of the whole periods. The method also includes repeating at least one of steps a) to c) and at each repetition shifting a start of the counting of step a) by at least one period of the reference signal, and in steps b) and c) accounting for whole periods of the signal already counted during the at least one preceding group of steps a) and b). The method includes determining a second average of the first averages, and determining the frequency of the signal from the second average and the frequency of the reference signal.

公开(公告)号：US09660034B1

公开(公告)日：2017-05-23

申请号：US15229746

申请日：2016-08-05

Applicant: STMicroelectronics SA

Inventor： Philippe Galy

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L29/1083 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1218 ,  H01L29/7838 ,  H01L29/78648

Abstract: An integrated circuit includes SOI-type MOS transistors on insulator, with a first well capable of being biased located under the insulator. The first wells are doped with a first conductivity type. Each first well includes, under the insulator of each transistor, a back gate region that is more heavily doped than the first well. The first wells are separated from each other by inclusion in in a second well that is also capable of being biased. The second well is doped with a second conductivity type.

公开(公告)号：US09653476B2

公开(公告)日：2017-05-16

申请号：US13933441

申请日：2013-07-02

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/12 ,  H01L27/02

CPC classification number: H01L27/1203 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it and a ground plane disposed under the layer. A well is disposed under the plane and a first trench is at the periphery of the transistor and extends through the layer into the well. There is a substrate under the well and a p-n diode on a side of the transistor. The diode comprises first and second zones of opposite doping and the first zone is configured for electrical connection to a first electrode of the transistor. The first and second zones are coplanar with the plane and a second trench for separating the first and second zones. The second trench extends through the layer into the plane to a depth less than an interface between the plane and the well. There is a third zone under the second trench forming a junction between the zones.