公开(公告)号：US20150363534A1

公开(公告)日：2015-12-17

申请号：US14301338

申请日：2014-06-11

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Kuo-Hsun HUANG ,  Hsi-Chang Chang ,  Chao-Yao Chiang ,  Chien-Hung Chen

IPC: G06F17/50

CPC classification number: G03F7/70441

Abstract: A method for post-OPC verification including of several steps is provided. First, a pre-OPC layout of an integrated circuit (IC) is received. Then, a first OPC procedure is performed to obtain a post-OPC layout of the IC. After that, a first extraction process is performed on the pre-OPC layout and a second extraction process is performed on the post-OPC layout to respectively obtain a first netlist and a second netlist by using a processor. Next, a verification process is performed by using the processor to determine whether an electrical network of the first netlist and an electrical network of the second netlist are identical. The verification process is then terminated if the electrical network of the first netlist and the electrical network of the second netlist are identical. An apparatus for post-OPC verification is also provided.

Abstract translation: 提供了一种用于后OPC验证的方法，包括几个步骤。 首先，接收到集成电路（IC）的OPC前布局。 然后，执行第一个OPC过程以获得IC的后OPC布局。 之后，对OPC前布局执行第一提取处理，并且在OPC后布局上执行第二提取处理，以通过使用处理器分别获得第一网表和第二网表。 接下来，通过使用处理器来确定第一网表的电网络和第二网表的电网是否相同来执行验证过程。 如果第一网表的电网和第二网表的电网相同，则终止验证过程。 还提供了用于后OPC验证的装置。

公开(公告)号：US20150332449A1

公开(公告)日：2015-11-19

申请号：US14281881

申请日：2014-05-19

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Te-Hsien HSIEH ,  Ming-Jui CHEN ,  Cheng-Te WANG ,  Jing-Yi LEE

IPC: G06T7/00 ,  G06K9/52

CPC classification number: G06T7/0004 ,  G03F1/36 ,  G03F7/70441 ,  G06K9/52

Abstract: A method for IC design is provided. Firstly, an IC design layout having a main feature with an original margin is received. Then, a first modified margin of the main feature is generated; and a first photolithography simulation procedure of the main feature with the first modified margin is performed to generate a first contour having a plurality of curves. Next, an equation of each of the curves is obtained; each equation of the curves is manipulated to obtain a vertex of each of the curves. After that, a first group of target points are assigned to the original margin. Each of the first group of target points respectively corresponds to one of the vertices. Finally, an optical proximity correction (OPC) procedure is performed by using the first group of target points to generate a second modified margin. An apparatus for IC design is also provided.

Abstract translation: 提供了一种IC设计方法。 首先，接收具有原始余量的主要特征的IC设计布局。 然后，生成主要特征的第一修改边缘; 并且执行具有第一修改余量的主要特征的第一光刻模拟程序以产生具有多个曲线的第一轮廓。 接着，求出各曲线的方程式， 操纵曲线的每个方程以获得每个曲线的顶点。 之后，将第一组目标点分配给原始边距。 第一组目标点中的每一个分别对应于一个顶点。 最后，通过使用第一组目标点来执行光学邻近校正（OPC）过程以产生第二修改余量。 还提供了用于IC设计的装置。

公开(公告)号：US09111850B2

公开(公告)日：2015-08-18

申请号：US14670440

申请日：2015-03-27

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chung-Sung Jang ,  Ming-Tse Lin ,  Yung-Chang Lin

IPC: G03F7/20 ,  H01L21/683 ,  H01L21/66

CPC classification number: H01L22/20 ,  G03F7/20 ,  G03F7/707 ,  G03F7/70783 ,  H01L21/6836 ,  H01L21/6838 ,  H01L22/12 ,  Y10T29/49764 ,  Y10T279/11

Abstract: A semiconductor process is described in this application. The process includes the following steps: providing a semiconductor substrate; measuring a warpage level of the semiconductor substrate; and holding the semiconductor substrate by providing at least one vacuum suction according to the warpage level, so that the semiconductor substrate is subjected to a plurality of varied suction intensities. The semiconductor substrate is held on a chuck having a plurality of holes grouped into a plurality of groups, and the sizes of the holes within different groups are different, wherein the sizes of the holes increase from a center toward an edge of the chuck, and the holes are arranged in a spiral.

Abstract translation: 在本申请中描述了半导体工艺。 该方法包括以下步骤：提供半导体衬底; 测量半导体衬底的翘曲程度; 并且通过根据翘曲水平提供至少一个真空吸力来保持半导体衬底，使得半导体衬底经受多个变化的吸入强度。 半导体基板被保持在具有分组为多组的多个孔的卡盘上，并且不同组内的孔的尺寸不同，其中孔的尺寸从卡盘的中心向边缘增加，并且 孔以螺旋状排列。

公开(公告)号：US09105355B2

公开(公告)日：2015-08-11

申请号：US13935487

申请日：2013-07-04

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Hsin-Wen Chen

IPC: G11C11/41 ,  G11C11/417 ,  G11C11/412 ,  G11C11/413 ,  G11C7/12

CPC classification number: G11C11/417 ,  G11C7/12 ,  G11C11/412 ,  G11C11/413

Abstract: A memory cell array includes a bit line, a complementary bit line, a first operation voltage supply circuit, a second operation voltage supply circuit, a first memory cell and a second memory cell. The first operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a first operation voltage. The second operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a second operation voltage. The first memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the first operation voltage. The second memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the second operation voltage. The first and second memory cells are located in a same column in the memory cell array.

Abstract translation: 存储单元阵列包括位线，互补位线，第一操作电压供给电路，第二操作电压供给电路，第一存储单元和第二存储单元。 第一操作电压供应电路电耦合到位线和互补位线，并用于提供第一操作电压。 第二操作电压供应电路电耦合到位线和互补位线，并用于提供第二操作电压。 第一存储单元电耦合到位线和互补位线，并用于接收第一操作电压。 第二存储单元电耦合到位线和互补位线，并用于接收第二操作电压。 第一和第二存储单元位于存储单元阵列中的同一列中。

公开(公告)号：US20150200144A1

公开(公告)日：2015-07-16

申请号：US14670440

申请日：2015-03-27

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： CHUNG-SUNG JANG ,  MING-TSE LIN ,  YUNG-CHANG LIN

IPC: H01L21/66 ,  H01L21/683

CPC classification number: H01L22/20 ,  G03F7/20 ,  G03F7/707 ,  G03F7/70783 ,  H01L21/6836 ,  H01L21/6838 ,  H01L22/12 ,  Y10T29/49764 ,  Y10T279/11

Abstract: A semiconductor process is described in this application. The process includes the following steps: providing a semiconductor substrate; measuring a warpage level of the semiconductor substrate; and holding the semiconductor substrate by providing at least one vacuum suction according to the warpage level, so that the semiconductor substrate is subjected to a plurality of varied suction intensities. The semiconductor substrate is held on a chuck having a plurality of holes grouped into a plurality of groups, and the sizes of the holes within different groups are different, wherein the sizes of the holes increase from a center toward an edge of the chuck, and the holes are arranged in a spiral.

Abstract translation: 在本申请中描述了半导体工艺。 该方法包括以下步骤：提供半导体衬底; 测量半导体衬底的翘曲程度; 并且通过根据翘曲水平提供至少一个真空吸力来保持半导体衬底，使得半导体衬底经受多个变化的吸入强度。 半导体基板被保持在具有分组为多组的多个孔的卡盘上，并且不同组内的孔的尺寸不同，其中孔的尺寸从卡盘的中心向边缘增加，并且 孔以螺旋状排列。

公开(公告)号：US09070612B2

公开(公告)日：2015-06-30

申请号：US14089716

申请日：2013-11-25

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Cheng-Hung Yu

IPC: H01L21/00 ,  H01L27/146

CPC classification number: H01L27/14685 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L2924/0002 ,  Y10T29/49 ,  H01L2924/00

Abstract: A method for fabricating an image sensor, wherein the method comprises steps as follows: Firstly, a transparent substrate is formed on a working substrate. Pluralities of micro lens are formed in the transparent substrate, wherein the lenses have a refraction ratio differing from that of the transparent substrate. Subsequently, a color filter is formed on the lenses. Afterward, the color filter is engaged with an image sensing device by flipping around the working substrate.

Abstract translation: 一种图像传感器的制造方法，其特征在于，包括以下步骤：首先，在工作基板上形成透明基板。 多个微透镜形成在透明基板中，其中透镜具有与透明基板不同的折射率。 随后，在透镜上形成滤色器。 之后，通过在工作基板周围翻转，滤色器与图像感测装置接合。

公开(公告)号：US20150093893A1

公开(公告)日：2015-04-02

申请号：US14044855

申请日：2013-10-02

Applicant: United Microelectronics Corporation

Inventor： Yi-Fang Tao ,  Ching-Wei Hsu ,  Hsin-Yu Chen ,  Tsun-Min Cheng ,  Yung-Chien Kung ,  Chi-Mao Hsu ,  Guo-Wei Chen ,  Huei-Ru Tsai ,  Jia-Rong Li

IPC: H01L21/768

CPC classification number: H01L21/76864 ,  H01L21/76873 ,  H01L21/76882

Abstract: In a process of forming a seed layer, particularly in a vertical trench or via, a semiconductor substrate having a dielectric structure and a hard mask structure thereon is provided. An opening is formed in the hard mask structure, and a trench or via is formed in the dielectric structure in communication with the opening, wherein an area of the opening is greater than that of an entrance of the trench or via. A seed layer is then deposited in the trench or via through the opening, and then subjected to a reflow process.

Abstract translation: 在形成种子层的过程中，特别是在垂直沟槽或通孔中，提供了具有电介质结构和硬掩模结构的半导体衬底。 在硬掩模结构中形成开口，并且在与开口连通的电介质结构中形成沟槽或通孔，其中开口的面积大于沟槽或通孔的入口面积。 然后将种子层沉积在沟槽或通孔中通过开口，然后进行回流处理。

公开(公告)号：US08956943B2

公开(公告)日：2015-02-17

申请号：US13902866

申请日：2013-05-27

Applicant: United Microelectronics Corporation

Inventor： Chien-Hung Chen ,  Tzu-Ping Chen ,  Yu-Jen Chang

IPC: H01L21/331 ,  H01L29/792 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833

Abstract: A method for manufacturing a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby forming a nitride layer on a sidewall of the gate conductive layer and extending into the opening.

Abstract translation: 公开了一种用于制造非易失性存储器的方法。 栅极结构形成在衬底上，并且包括栅极介电层和栅极导电层。 部分地去除栅介质层，从而在栅极导电层，基板和栅极电介质层之间形成对称的开口，并且在栅极电介质层的端侧形成空腔。 在栅极导电层的侧壁和底部上形成第一氧化物层，并且在衬底的表面上形成第二氧化物层。 形成覆盖栅极结构，第一和第二氧化物层和衬底并填充开口的氮化物材料层。 执行蚀刻处理以部分地去除氮化物材料层，从而在栅极导电层的侧壁上形成并延伸到开口中的氮化物层。

公开(公告)号：US08850370B2

公开(公告)日：2014-09-30

申请号：US14094806

申请日：2013-12-03

Applicant: United Microelectronics Corporation

Inventor： Chia-Chen Sun ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Yao-Chang Wang

IPC: G06F17/50 ,  H01L23/528

CPC classification number: G06F17/5081 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto. The layout method is then determining whether the first distance is larger than a first critical value. Later, when the first distance is larger than the first critical value, at least a closed loop dummy pattern is putted in one of the areas corresponding to the first distance between the pair of the circuit patterns. The closed loop dummy pattern is putted in a same layer with the circuit patterns, surrounds between the pair of circuit patterns and is insulated from the circuit patterns.

Abstract translation: 提供了半导体电路的布局方法。 布局方法是首先在基板上放置多个电路图案，其中第一距离是任何一个电路图案与与其相邻的其它电路图案之一之间的最大距离。 布局方法然后确定第一距离是否大于第一临界值。 之后，当第一距离大于第一临界值时，至少一个闭环虚拟图形被放置在对应于该对电路图形之间的第一距离的一个区域中。 闭环虚拟图案被放置在与电路图案相同的层中，围绕在一对电路图案之间并与电路图案绝缘。

公开(公告)号：US08804440B1

公开(公告)日：2014-08-12

申请号：US14225435

申请日：2014-03-26

Applicant: United Microelectronics Corporation

Inventor： Shi-Wen Chen ,  Hsin-Pang Lu ,  Chung-Cheng Tsai ,  Ya-Nan Mou

IPC: G11C7/10 ,  G11C5/14 ,  G11C7/06 ,  G11C11/4074 ,  G11C7/00

CPC classification number: G11C5/147 ,  G11C7/00 ,  G11C7/08 ,  G11C7/10 ,  G11C8/08 ,  G11C11/4074 ,  G11C16/30 ,  G11C29/021

Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Abstract translation: 电源电压产生电路包括比较单元，电压电平控制单元和电压调节器电路。 比较单元被配置为将存储器阵列的输入数据和输出数据彼此进行比较，从而生成比较结果，其中输出数据是存储在存储器阵列的多个存储器单元中的存储数据，该存储器单元根据根据 输入数据和比较结果表示输出数据和输入数据之间存在的不同位数。 电压电平控制单元被配置为根据比较结果产生控制信号。 电压调节器电路被配置为为存储器阵列提供电源电压，并根据控制信号调整电源电压的值。 还提供了用于存储器阵列的供应生成电路的存储器和操作方法。