公开(公告)号：US20240339501A1

公开(公告)日：2024-10-10

申请号：US18143095

申请日：2023-05-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Che-Hsien Lin ,  Te-Chang Hsu ,  Chun-Jen Huang ,  Chun-Chia Chen

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming a fin-shaped structure on the substrate, forming a gate structure on the fin-shaped structure, removing the fin-shaped structure to form a recess, forming a first epitaxial layer in the recess adjacent to the gate structure, and then forming a second epitaxial layer on the first epitaxial layer. Preferably, the semiconductor device further includes a first protrusion on one side of the first epitaxial layer and a second protrusion on another side of the first epitaxial layer.

公开(公告)号：US20240339331A1

公开(公告)日：2024-10-10

申请号：US18143076

申请日：2023-05-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Guang-Yu Lo ,  Chun-Tsen Lu

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78

CPC classification number: H01L21/31144 ,  H01L21/02123 ,  H01L21/308 ,  H01L29/785 ,  H01L29/41791

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising a medium-voltage (MV) region and a low-voltage (LV) region, forming a first gate structure and a second gate structure on the MV region and a second gate structure on the LV region, forming a patterned mask on the MV region as the patterned mask covers the first gate structure and the second gate structure and exposes the substrate between the first gate structure and the second gate structure, and then forming a first epitaxial layer between the first gate structure and the second gate structure.

公开(公告)号：US12113098B2

公开(公告)日：2024-10-08

申请号：US18123972

申请日：2023-03-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Kuang-Pi Lee ,  Wen-Jung Liao

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L27/0605 ,  H01L27/0629

Abstract: A capacitor structure includes an insulation layer and a capacitor unit disposed on the insulation layer. The capacitor unit includes a first electrode, a second electrode, a first dielectric layer, and a patterned conductive layer. The second electrode is disposed above the first electrode in a vertical direction. The first dielectric layer is disposed between the first electrode and the second electrode in the vertical direction. The patterned conductive layer is disposed between first electrode and the second electrode, the patterned conductive layer is electrically connected with the first electrode, and the first dielectric layer surrounds the patterned conductive layer in a horizontal direction.

公开(公告)号：US12112981B2

公开(公告)日：2024-10-08

申请号：US17679133

申请日：2022-02-24

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/522 ,  H01L27/12

CPC classification number: H01L21/7682 ,  H01L21/76897 ,  H01L23/5222 ,  H01L27/1207

Abstract: A semiconductor device is provided. The semiconductor device includes a device substrate, having a device structure layer and a buried dielectric layer, wherein the buried dielectric layer is disposed on a semiconductor layer of the device structure layer and the device substrate comprises a device structure. A metal layer is disposed on the buried dielectric layer and surrounded by a first inter-layer dielectric (ILD) layer. A region of the metal layer has a plurality of openings. The buried dielectric layer has an air gap under and exposing the region of the metal layer with the openings, wherein the air gap is located above the device structure in the device substrate. A second ILD layer is disposed on the metal layer and sealing the air gap at the openings of the metal layer.

公开(公告)号：US20240334850A1

公开(公告)日：2024-10-03

申请号：US18741808

申请日：2024-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/8833 ,  H10B63/00 ,  H10N70/023 ,  H10N70/063 ,  H10N70/841

Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.

公开(公告)号：US20240332086A1

公开(公告)日：2024-10-03

申请号：US18739261

申请日：2024-06-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Po-Ching Su ,  Yu-Fu Wang ,  Min-Hua Tsai ,  Ti-Bin Chen ,  Chih-Chiang Wu ,  Tzu-Chin Wu

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/4232 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

公开(公告)号：US12108691B2

公开(公告)日：2024-10-01

申请号：US18324173

申请日：2023-05-26

Applicant: United Microelectronics Corp.

Inventor： Chich-Neng Chang ,  Da-Jun Lin ,  Shih-Wei Su ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/24 ,  H10B63/30 ,  H10N70/063 ,  H10N70/826 ,  H10N70/841

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

公开(公告)号：US12107157B2

公开(公告)日：2024-10-01

申请号：US18223543

申请日：2023-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/20 ,  H01L21/308 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/66462

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

公开(公告)号：US12107151B2

公开(公告)日：2024-10-01

申请号：US18208895

申请日：2023-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Tsuo-Wen Lu ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/311

CPC classification number: H01L29/6656 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/31116

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on sidewalls of gate structure, a second spacer on sidewalls of the first spacer, a polymer block adjacent to the first spacer and on a corner between the gate structure and the substrate, an interfacial layer under the polymer block, and a source/drain region adjacent to two sides of the first spacer. Preferably, the polymer block is surrounded by the first spacer, the interfacial layer, and the second spacer.

公开(公告)号：US20240324472A1

公开(公告)日：2024-09-26

申请号：US18679437

申请日：2024-05-30

Applicant: United Microelectronics Corp.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Si-Han Tsai ,  Che-Wei Chang ,  Jing-Yin Jhang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.