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公开(公告)号：US20150100848A1
公开(公告)日：2015-04-09
申请号：US14048830
申请日：2013-10-08
Applicant: Advanced Micro Devices, Inc.
Inventor： John Kalamatianos , Johnsy Kanjirapallil John , Robert Gelinas , Vilas K. Sridharan , Phillip E. Nevius
CPC classification number: G06F11/1008 , G11C11/41 , G11C29/42 , G11C29/52 , G11C29/78 , G11C2029/0409
Abstract: Hard errors in the memory array can be detected and corrected in real-time using reusable entries in an error status buffer. Data may be rewritten to a portion of a memory array and a register in response to a first error in data read from the portion of the memory array. The rewritten data may then be written from the register to an entry of an error status buffer in response to the rewritten data read from the register differing from the rewritten data read from the portion of the memory array.
Abstract translation: 可以使用错误状态缓冲区中的可重用条目实时检测和校正存储器阵列中的硬错误。 响应于从存储器阵列的部分读取的数据中的第一个错误，数据可以重写到存储器阵列和寄存器的一部分。 然后可以将重写的数据从寄存器写入错误状态缓冲器的条目，以响应于从寄存器读取的重写数据与从存储器阵列的部分读取的重写数据不同。
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公开(公告)号：US20140359221A1
公开(公告)日：2014-12-04
申请号：US13907209
申请日：2013-05-31
Applicant: Advanced Micro Devices, Inc.
Inventor： John Kalamatianos , Paul E. Keltcher
IPC: G06F12/08
CPC classification number: G06F12/0811 , G06F12/0862 , G06F2212/6026
Abstract: The present application describes some embodiments of a prefetcher that tracks multiple stride sequences for prefetching. Some embodiments of the prefetcher implement a method including generating a sum-of-strides for each of a plurality of stride lengths that are larger than one by summing a number of previous strides that is equal to the stride length. Some embodiments of the method also include prefetching data in response to repetition of one or more of the sum-of-strides for one or more of the plurality of stride lengths.
Abstract translation: 本申请描述了预取器的一些实施例，该预取器跟踪用于预取的多个步幅序列。 预取器的一些实施例实现一种方法，该方法包括通过对等于步幅长度的先前步幅的数量进行求和来产生大于1的多个步幅长度中的每一个步长的总和。 该方法的一些实施例还包括响应于对于多个步幅长度中的一个或多个步长的一个或多个步数的重复来预取数据。
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83.发明申请公开(公告)号：US20140237212A1
公开(公告)日：2014-08-21
申请号：US13773166
申请日：2013-02-21
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Alok Garg , Sharad Bade , John Kalamatianos
IPC: G06F12/02
CPC classification number: G06F12/0215 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F12/0862 , G06F2212/6026
Abstract: A method, an apparatus, and a non-transitory computer readable medium for tracking prefetches generated by a stride prefetcher are presented. Responsive to a prefetcher table entry for an address stream locking on a stride, prefetch suppression logic is updated and prefetches from the prefetcher table entry are suppressed when suppression is enabled for that prefetcher table entry. A stride is a difference between consecutive addresses in the address stream. A prefetch request is issued from the prefetcher table entry when suppression is not enabled for that prefetcher table entry.
Abstract translation: 提出了一种用于跟踪由步幅预取器产生的预取的方法，装置和非暂时计算机可读介质。 响应于在步幅上锁定的地址流的预取器表条目，预取抑制逻辑被更新，并且对于该预取器表条目启用抑制时，来自预取器表条目的预取被抑制。 步幅是地址流中连续地址之间的差异。 当预取器表项不启用抑制时，从预取器表项发出预取请求。
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公开(公告)号：US20140129780A1
公开(公告)日：2014-05-08
申请号：US13671801
申请日：2012-11-08
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Sharad Dilip Bade , Alok Garg , John Kalamatianos , Paul Keltcher , Marius Evers , Chitresh Narasimhaiah
IPC: G06F12/08
CPC classification number: G06F12/0862 , G06F9/3842 , G06F11/30 , G06F2212/6024 , G06F2212/6026 , Y02D10/13
Abstract: Methods and systems for prefetching data for a processor are provided. A system is configured for and a method includes selecting one of a first prefetching control logic and a second prefetching control logic of the processor as a candidate feature, capturing the performance metric of the processor over an inactive sample period when the candidate feature is inactive, capturing a performance metric of the processor over an active sample period when the candidate feature is active, comparing the performance metric of the processor for the active and inactive sample periods, and setting a status of the candidate feature as enabled when the performance metric in the active period indicates improvement over the performance metric in the inactive period, and as disabled when the performance metric in the inactive period indicates improvement over the performance metric in the active period.
Abstract translation: 提供了用于为处理器预取数据的方法和系统。 系统被配置用于并且方法包括选择处理器的第一预取控制逻辑和第二预取控制逻辑之一作为候选特征，当候选特征不活动时，在非活动采样周期捕获处理器的性能度量， 当候选特征处于活动状态时，在活动采样周期捕获处理器的性能度量，比较处于活动和非活动采样周期的处理器的性能度量，并且将候选特征的状态设置为使能时的性能度量 活动期间表示在非活动期间的性能指标改善，当非活动期间的性能指标表示改善了活动期间的绩效指标时被禁用。
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公开(公告)号：US20250004963A1
公开(公告)日：2025-01-02
申请号：US18217079
申请日：2023-06-30
Applicant: Advanced Micro Devices, Inc.
Inventor： William Peter Ehrett , Anthony Gutierrez , Vedula Venkata Srikant Bharadwaj , Karthik Ramu Sangaiah , Prachi Shukla , Sriseshan Srikanth , Ganesh Dasika , John Kalamatianos
IPC: G06F13/36
Abstract: A semiconductor device, referred to herein as a Globally Interconnected Operations (GIO) layer, provides global operations in the form of global data reduction for one or more PE arrays. The GIO layer includes processing elements that perform global data reduction on processing results from one or more PE arrays. The GIO layer includes connectors that allow it to be arranged in a 3D stack with one or more PE arrays, for example, on top of or beneath a PE array. This allows reduction operations to be implemented across PE arrays using an efficient topology with superior flexibility, scalability, latency and/or power characteristics that is customizable for particular use cases at assembly time, without requiring costly and time-consuming redesign of PE arrays, and without being constrained by particular PE array designs.
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Patent Agency Ranking
公开(公告)号：US12153926B2
公开(公告)日：2024-11-26
申请号：US18393657
申请日：2023-12-21
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： John Kalamatianos , Michael T. Clark , Marius Evers , William L. Walker , Paul Moyer , Jay Fleischman , Jagadish B. Kotra
Abstract: Processor-guided execution of offloaded instructions using fixed function operations is disclosed. Instructions designated for remote execution by a target device are received by a processor. Each instruction includes, as an operand, a target register in the target device. The target register may be an architected virtual register. For each of the plurality of instructions, the processor transmits an offload request in the order that the instructions are received. The offload request includes the instruction designated for remote execution. The target device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.
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公开(公告)号：US20230376420A1
公开(公告)日：2023-11-23
申请号：US18302968
申请日：2023-04-19
Applicant: Advanced Micro Devices, Inc.
Inventor： Susumu Mashimo , John Kalamatianos
IPC: G06F12/0862 , G06F12/0877 , G06F9/30 , G06F18/214
CPC classification number: G06F12/0862 , G06F12/0877 , G06F9/30047 , G06F9/30101 , G06F9/30036 , G06F18/214 , G06F2212/6024
Abstract: A method includes recording a first set of consecutive memory access deltas, where each of the consecutive memory access deltas represents a difference between two memory addresses accessed by an application, updating values in a prefetch training table based on the first set of memory access deltas, and predicting one or more memory addresses for prefetching responsive to a second set of consecutive memory access deltas and based on values in the prefetch training table.
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公开(公告)号：US11726917B2
公开(公告)日：2023-08-15
申请号：US16927786
申请日：2020-07-13
Applicant: Advanced Micro Devices, Inc.
Inventor： Susumu Mashimo , John Kalamatianos
IPC: G06F12/0862 , G06F12/0877 , G06F9/30 , G06K9/62
CPC classification number: G06F12/0862 , G06F9/30036 , G06F9/30047 , G06F9/30101 , G06F12/0877 , G06K9/6256 , G06F2212/6024
Abstract: A method includes recording a first set of consecutive memory access deltas, where each of the consecutive memory access deltas represents a difference between two memory addresses accessed by an application, updating values in a prefetch training table based on the first set of memory access deltas, and predicting one or more memory addresses for prefetching responsive to a second set of consecutive memory access deltas and based on values in the prefetch training table.
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公开(公告)号：US11658681B2
公开(公告)日：2023-05-23
申请号：US17348202
申请日：2021-06-15
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Greg Sadowski , John Kalamatianos
CPC classification number: H03M7/6047 , H03M5/04 , H04B1/04 , H04B1/16 , H04B3/54
Abstract: Various energy efficient data encoding schemes and computing devices are disclosed. In one aspect, a method of transmitting data from a transmitter to a receiver connected by plural wires is provided. The method includes sending from the transmitter on at least one but not all of the wires a first wave form that has first and second signal transitions. The receiver receives the first waveform and measures a first duration between the first and second signal transitions using a locally generated clock signal not received from the transmitter. The first duration is indicative of a first particular data value.
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公开(公告)号：US11656945B2
公开(公告)日：2023-05-23
申请号：US17133843
申请日：2020-12-24
Applicant: Advanced Micro Devices, Inc.
Inventor： John Kalamatianos , Nuwan Jayasena , Sudhanva Gurumurthi , Shaizeen Aga , Shrikanth Ganapathy
CPC classification number: G06F11/141 , G06F9/3877
Abstract: Methods and processing devices are provided for error protection to support instruction replay for executing idempotent instructions at a processing in memory PIM device. The processing apparatus includes a PIM device configured to execute an idempotent instruction. The processing apparatus also includes a processor, in communication with the PIM device, configured to issue the idempotent instruction to the PIM device for execution at the PIM device and reissue the idempotent instruction to the PIM device when one of execution of the idempotent instruction at the PIM device results in an error and a predetermined latency period expires from when the idempotent instruction is issued.
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