公开(公告)号：US06857043B1

公开(公告)日：2005-02-15

申请号：US09761609

申请日：2001-01-16

申请人： Andy L. Lee ,  Brian Johnson ,  Richard G. Cliff

发明人： Andy L. Lee ,  Brian Johnson ,  Richard G. Cliff

IPC分类号： G06F5/10 ,  G06F5/14 ,  G06F12/00

CPC分类号： G06F5/14 ,  G06F2205/102

摘要： First-in/first-out (“FIFO”) memory circuitry includes first and second Gray-code-based counters for respectively counting write and read clock signals. A Gray code subtractor subtracts from one another the counts output by the counters. Shift register circuitry shifts in successive data words in synchronism with the write clock signal. The shift register circuitry includes selection circuitry configured to select one of the data words based on a Gray code decoding of information from the subtractor. Circuitry may also be included to monitor the information from the subtractor to detect full or empty conditions of the shift register circuitry.

摘要翻译： 先进先出（“FIFO”）存储器电路包括用于分别计数写入和读取时钟信号的第一和第二基于格雷码的计数器。 格雷码减法器从计数器输出的计数相减。 移位寄存器电路与写时钟信号同步地移位连续的数据字。 移位寄存器电路包括选择电路，其被配置为基于来自减法器的信息的格雷码解码来选择数据字之一。 也可以包括电路以监视来自减法器的信息以检测移位寄存器电路的全部或空的条件。

公开(公告)号：US20050030800A1

公开(公告)日：2005-02-10

申请号：US10634130

申请日：2003-08-04

申请人： Brian Johnson ,  Stephen Hudgens

发明人： Brian Johnson ,  Stephen Hudgens

IPC分类号： G11C16/02 ,  H01L45/00 ,  G11C29/00

CPC分类号： G11C13/0004 ,  G11C2213/52 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144

摘要： A phase change layer may switch between more and less conductive states in response to electrical stimulation. The phase change layer may be positioned over a non-switching ovonic material which acts as an electrode, a resistive heater, and an insulating barrier. The phase change layer may be positioned over a non-switching ovonic material which acts as an electrode, a resistive heater, and a thermal barrier.

摘要翻译： 响应于电刺激，相变层可以在越来越少的导电状态之间切换。 相变层可以位于用作电极，电阻加热器和绝缘屏障的非开关式超声波材料上。 相变层可以位于作为电极，电阻加热器和热障壁的非切换式超声波材料上。

公开(公告)号：US20050007807A1

公开(公告)日：2005-01-13

申请号：US10910980

申请日：2004-08-03

申请人： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

发明人： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

IPC分类号： G11C5/00 ,  H05K1/18 ,  G11C7/00

CPC分类号： H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

摘要： The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

公开(公告)号：US06836166B2

公开(公告)日：2004-12-28

申请号：US10339752

申请日：2003-01-08

申请人： Feng Lin ,  Brent Keeth ,  Brian Johnson

发明人： Feng Lin ,  Brent Keeth ,  Brian Johnson

IPC分类号： H03L706

CPC分类号： G11C7/222 ,  G11C7/1072 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： A synchronization circuit includes a first and second phase-shifting path circuit, with each generates a phase-shifted signal responsive to an input signal and the phase-shifted signal having respective fine and coarse phase shifts relative to the input signal. Each phase-shifting path circuit adjusts the coarse and fine phase shifts responsive to control signals. A selection circuit outputs one of the phase-shifted signals responsive to a selection signal. A control circuit monitors a phase shift between the input signal and the output phase-shifted signal and develops the selection and control signals to select one of the phase-shifting path circuits and to adjust the fine phase shift of the selected path circuit and the fine and coarse phase shifts of the other path circuit. When the fine delay of the selected phase-shifting path circuit has a threshold value, the control circuit develops the selection signal to select the other phase-shifting circuit.

摘要翻译： 同步电路包括第一和第二移相路径电路，每个产生响应于输入信号的相移信号，并且相移信号相对于输入信号具有相应的精细和粗略的相移。 每个移相路径电路响应于控制信号调整粗略和精细的相移。 选择电路响应于选择信号输出一个相移信号。 控制电路监视输入信号和输出相移信号之间的相移，并产生选择和控制信号以选择一个相移路径电路并调整所选路径电路的精细相移和精细 和另一路径电路的粗相移。 当所选择的移相路径电路的精细延迟具有阈值时，控制电路产生选择信号以选择另一个移相电路。

公开(公告)号：US06807500B2

公开(公告)日：2004-10-19

申请号：US10292654

申请日：2002-11-13

申请人： Brian Johnson ,  Brent Keeth

发明人： Brian Johnson ,  Brent Keeth

IPC分类号： G06F112

CPC分类号： G11C29/028 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/50012 ,  G11C2207/2254

摘要： A method and apparatus for calibrating a data path of a digital circuit uses an even bit pseudo-random calibration pattern. A portion of the pattern is captured in a capture period and used to predict a next arriving portion of the calibration pattern. The next arriving portion of the calibration pattern is captured and then compared to the predicted pattern in a compare period, and the result of the comparison is used to relatively time data arriving in the data path to a clocking signal which clocks in the data. The time duration of the compare period may be varied to ensure that all possible bits of the calibration pattern are used in the calibration procedure.

摘要翻译： 用于校准数字电路的数据路径的方法和装置使用偶数位伪随机校准模式。 在捕获周期中捕获图案的一部分，并用于预测校准图案的下一个到达部分。 捕获校准图案的下一个到达部分，然后在比较周期中与预测图案进行比较，并将比较结果用于到数据路径中的相对时间数据到数据中的时钟信号。 可以改变比较周期的持续时间以确保在校准过程中使用校准图案的所有可能位。

公开(公告)号：US06751717B2

公开(公告)日：2004-06-15

申请号：US09767490

申请日：2001-01-23

申请人： Brian Johnson

发明人： Brian Johnson

IPC分类号： G06F1200

CPC分类号： G06F13/28

摘要： The present invention coordinates the execution of commands, received in response to a continuous system clock, with the receipt of data in response to a burst clock. Command capture logic receives command information in response to the system clock. A storage element is responsive to the command capture logic for storing certain command information such as write commands. A two stage pipeline receives the command information from the storage element in response to the burst clock and outputs the command information in response to the system clock. Methods of operating the apparatus are also disclosed.

摘要翻译： 本发明协调响应于连续系统时钟接收的响应于突发时钟的数据的接收的命令的执行。 命令捕获逻辑响应系统时钟接收命令信息。 存储元件响应于用于存储诸如写命令之类的某些命令信息的命令捕获逻辑。 双级流水线响应于突发时钟从存储元件接收命令信息，并根据系统时钟输出命令信息。 还公开了操作该装置的方法。

公开(公告)号：US06697926B2

公开(公告)日：2004-02-24

申请号：US09874289

申请日：2001-06-06

申请人： Brian Johnson ,  Brent Keeth ,  Troy A. Manning

发明人： Brian Johnson ,  Brent Keeth ,  Troy A. Manning

IPC分类号： G06F1200

CPC分类号： G11C29/028 ,  G06F13/1694 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  G11C11/401 ,  G11C29/50012 ,  G11C2207/2254

摘要： A method and apparatus for accurately determining the actual arrival of data at a memory device relative to the write clock to accurately align the start of data capture and the arrival of the data at the memory device is disclosed. The actual time of arrival of data at the inputs to a memory device is determined by sending back-to-back write commands along with a predetermined data pattern to the memory device. The data pattern is stored in a register and any difference between the predicted arrival time of the data and the actual arrival time of the data is determined by logic circuitry. Any determined difference can then be compensated for by delaying the start of the capture of the data at the memory device, thereby accurately aligning the start of the data capture and the arrival of the data at the memory device.

摘要翻译： 公开了一种用于准确地确定数据在存储器件相对于写入时钟的实际到达以精确对准数据捕获的开始和数据到存储器件的方法和装置。 将数据到输入到存储器件的实际时间通过与存储器件一起发送背靠背写入命令以及预定数据模式来确定。 数据模式存储在寄存器中，数据的预计到达时间与数据的实际到达时间之间的任何差异由逻辑电路确定。 然后可以通过延迟在存储器件处捕获数据的开始来补偿任何确定的差异，从而将数据捕获的开始和数据的到达准确地对准存储器件。

公开(公告)号：US06665223B2

公开(公告)日：2003-12-16

申请号：US10278509

申请日：2002-10-22

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C700

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US06658523B2

公开(公告)日：2003-12-02

申请号：US09804221

申请日：2001-03-13

申请人： Jeffery W. Janzen ,  Brent Keeth ,  Kevin J. Ryan ,  Troy A. Manning ,  Brian Johnson

发明人： Jeffery W. Janzen ,  Brent Keeth ,  Kevin J. Ryan ,  Troy A. Manning ,  Brian Johnson

IPC分类号： G06F1200

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.

公开(公告)号：US06522172B2

公开(公告)日：2003-02-18

申请号：US09812757

申请日：2001-03-20

申请人： Brent Keeth ,  Brian Johnson

发明人： Brent Keeth ,  Brian Johnson

IPC分类号： H03K1903

CPC分类号： H03K3/356121 ,  H03K3/012

摘要： A circuit having a data input pin for receiving a data signal, a clock input for receiving a clock signal and having a low setup time and a zero hold time is comprised of an input stage for periodically connecting a sampling device to the data input pin in response to the clock signal. An evaluation stage, responsive to the clock signal, evaluates the charge collected by the device at a time the device is disconnected from the data input pin. The evaluation stage produces a signal representative of the sampled charge. An output stage, responsive to the clock signal and the produced signal, outputs a data signal representative of the sampled data signal. The circuit may have a single data path and a single charge accumulating device such that an output signal representative of the sampled data signal is available on either the rising or the falling edge of the clock signal. Alternatively, multiple data paths may be provided as well as multiple charge accumulating devices so that data signals representative of the sampled data may be output on both the rising and the falling edge of the clock signal. The circuit can be operated as either a latch or a register. A method of operating a data acquisition and retention circuit having a zero hold time and of the type useful for receiving signals from a high speed bus is also disclosed.

摘要翻译： 具有用于接收数据信号的数据输入引脚的电路，用于接收时钟信号并具有低建立时间和零保持时间的时钟输入包括用于将采样装置周期性地连接到数据输入引脚的输入级 响应时钟信号。 响应于时钟信号的评估阶段评估设备在与数据输入引脚断开连接时收集的电荷。 评估阶段产生代表采样电荷的信号。 响应于时钟信号和产生的信号的输出级输出表示采样数据信号的数据信号。 电路可以具有单个数据路径和单个电荷累积装置，使得表示采样数据信号的输出信号在时钟信号的上升沿或下降沿都可用。 或者，可以提供多个数据路径以及多个电荷累积装置，使得表示采样数据的数据信号可以在时钟信号的上升沿和下降沿两者上输出。 该电路可以作为锁存器或寄存器来操作。 还公开了一种操作具有零保持时间的数据采集和保持电路以及用于从高速总线接收信号的类型的方法。