公开(公告)号：US20120326236A1

公开(公告)日：2012-12-27

申请号：US13604340

申请日：2012-09-05

申请人： Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

发明人： Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L2029/7858

摘要： A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.

摘要翻译： 一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成 沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。 该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻 沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。

公开(公告)号：US20120306000A1

公开(公告)日：2012-12-06

申请号：US13118689

申请日：2011-05-31

申请人： Josephine B. Chang ,  Paul C. Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

发明人： Josephine B. Chang ,  Paul C. Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/0207 ,  H01L29/66545

摘要： A method includes defining active regions on a substrate, forming a dummy gate stack material over exposed portions of the active regions of the substrate and non-active regions of the substrate, removing portions of the dummy gate stack material to expose portions of the active regions and non-active regions of the substrate and define dummy gate stacks, forming a gap-fill dielectric material over the exposed portions of the substrate and the source and drain regions, removing portions of the gap-fill dielectric material to expose the dummy gate stacks, removing the dummy gate stacks to form dummy gate trenches, forming dividers within the dummy gate trenches, depositing gate stack material inside the dummy gate trenches, over the dividers, and the gap-fill dielectric material, and removing portions of the gate stack material to define gate stacks.

摘要翻译： 一种方法包括在衬底上限定有源区域，在衬底的有源区域和衬底的非有源区域的暴露部分上形成虚拟栅极堆叠材料，去除虚拟栅极堆叠材料的部分以暴露部分有源区域 和非活性区域，并且限定伪栅极堆叠，在衬底和源极和漏极区域的暴露部分上形成间隙填充电介质材料，去除间隙填充电介质材料的部分以暴露伪栅极堆叠 ，去除虚拟栅极堆叠以形成伪栅极沟槽，在虚拟栅极沟槽内形成分隔线，在虚拟栅极沟槽内部，在分隔器上方形成栅极堆叠材料，以及间隙填充电介质材料，以及去除栅极堆叠材料的部分 定义栅极堆叠。

公开(公告)号：US20120292597A1

公开(公告)日：2012-11-22

申请号：US13562827

申请日：2012-07-31

申请人： Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

发明人： Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC分类号： H01L29/775

CPC分类号： H01L29/1606 ,  B82Y10/00 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/66431 ,  H01L29/66742 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/78684 ,  H01L51/0048

摘要： A semiconductor device includes a carbon layer disposed on a substrate, a gate stack disposed on a portion of the carbon layer, a first cavity defined by the carbon layer and the substrate, a second cavity defined by the carbon layer and the substrate, a source region including a first conductive contact disposed in the first cavity, a drain region including a second conductive contact disposed in the second cavity.

摘要翻译： 半导体器件包括设置在基底上的碳层，设置在碳层的一部分上的栅极叠层，由碳层和衬底限定的第一腔，由碳层和衬底限定的第二腔，源 区域，包括设置在第一腔中的第一导电触点，漏区，包括设置在第二腔中的第二导电触点。

公开(公告)号：US20120286377A1

公开(公告)日：2012-11-15

申请号：US13103193

申请日：2011-05-09

申请人： Josephine B. Chang ,  Sebastian U. Engelmann ,  Michael A. Guillorn ,  Fei Liu ,  Conal E. Murray

发明人： Josephine B. Chang ,  Sebastian U. Engelmann ,  Michael A. Guillorn ,  Fei Liu ,  Conal E. Murray

IPC分类号： H01L29/84 ,  H01L21/3105 ,  H01L29/06

CPC分类号： H01L29/84 ,  B81B3/0072 ,  B81B2203/0109 ,  B81B2203/0307 ,  H01L29/0673

摘要： Improved nano-electromechanical system devices and structures and systems and techniques for their fabrication. In one embodiment, a structure comprises an underlying substrate separated from first and second anchor points by first and second insulating support points, respectively. The first and second anchor points are joined by a beam. First and second deposition regions overlie the first and second anchor points, respectively, and the first and second deposition regions exert compression on the first and second anchor points, respectively. The compression on the first and second anchor points causes opposing forces on the beam, subjecting the beam to a tensile stress. The first and second deposition regions suitably exhibit an internal tensile stress having an achievable maximum varying with their thickness, so that the tensile stress exerted on the beam depends at least on part on the thickness of the first and second deposition regions.

摘要翻译： 改进的纳米机电系统设备及其制造的结构及系统和技术。 在一个实施例中，结构包括分别通过第一和第二绝缘支撑点从第一和第二锚定点分离的下面的基底。 第一和第二锚定点通过梁连接。 第一和第二沉积区域分别覆盖在第一和第二锚定点上，并且第一和第二沉积区域分别在第一和第二锚定点上施加压缩。 第一和第二锚固点上的压缩在梁上产生相反的力，使梁受到拉伸应力。 第一和第二沉积区域适当地呈现具有随其厚度变化的可实现最大值的内部拉伸应力，使得施加在梁上的拉伸应力至少部分地取决于第一和第二沉积区域的厚度。

公开(公告)号：US08242485B2

公开(公告)日：2012-08-14

申请号：US12762832

申请日：2010-04-19

申请人： Josephine B. Chang ,  Christian Lavoie ,  Zhen Zhang

发明人： Josephine B. Chang ,  Christian Lavoie ,  Zhen Zhang

IPC分类号： H01L29/06 ,  H01L21/44

CPC分类号： H01L29/1606 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/45 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78618 ,  H01L29/78684 ,  H01L51/0048 ,  H01L51/105

摘要： Electronic devices having carbon-based materials and techniques for making contact to carbon-based materials in electronic devices are provided. In one aspect, a device is provided having a carbon-based material; and at least one electrical contact to the carbon-based material comprising a metal silicide, germanide or germanosilicide. The carbon-based material can include graphene or carbon nano-tubes. The device can further include a segregation region, having an impurity, separating the carbon-based material from the metal silicide, germanide or germanosilicide, wherein the impurity has a work function that is different from a work function of the metal silicide, germanide or germanosilicide. A method for fabricating the device is also provided.

摘要翻译： 提供了具有碳基材料的电子器件和用于与电子器件中的碳基材料接触的技术。 一方面，提供一种具有碳基材料的装置; 以及与包含金属硅化物，锗化锗或锗硅化物的碳基材料的至少一个电接触。 碳基材料可以包括石墨烯或碳纳米管。 该装置还可以包括具有杂质的偏析区域，从金属硅化物，锗化锗或锗硅化物中分离碳基材料，其中杂质具有不同于金属硅化物，锗化锗或锗硅酸盐的功函数 。 还提供了一种用于制造该装置的方法。

公开(公告)号：US20120199941A1

公开(公告)日：2012-08-09

申请号：US13365764

申请日：2012-02-03

申请人： Stephen W. Bedell ,  Josephine B. Chang ,  Chung-Hsun Lin

发明人： Stephen W. Bedell ,  Josephine B. Chang ,  Chung-Hsun Lin

IPC分类号： H01L29/06

CPC分类号： H01L29/66477 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7849

摘要： A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.

摘要翻译： 公开了一种制造集成电路的方法和在应力衬垫上具有硅的集成电路。 在一个实施例中，该方法包括提供包括嵌入式一次性层的半导体衬底，以及去除该一次性层的至少一部分以在衬底内形成空隙。 该方法还包括在该空隙中沉积材料以形成应力衬垫，以及在衬底的外部半导体层上形成晶体管。 该半导体层将晶体管与应力衬垫分开。 在一个实施例中，衬底包括隔离区; 并且所述去除包括在所述隔离区域中形成凹部，以及经由所述凹部去除所述一次性层的至少一部分。 在一个实施例中，沉积包括通过凹部将材料沉积在空隙中。 端盖可以形成在应力衬垫的端部处的凹部中。

公开(公告)号：US08178400B2

公开(公告)日：2012-05-15

申请号：US12567963

申请日：2009-09-28

申请人： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Amlan Majumdar

发明人： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Amlan Majumdar

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7391 ,  H01L29/66356

摘要： A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.

摘要翻译： 一种半导体制造方法，包括在基板上沉积虚拟栅极层，图案化虚拟栅极层，在伪栅极层上沉积硬掩模层，图案化硬掩模层，在凹模栅极层附近蚀刻到衬底中的凹陷， 将半导体材料进入凹部，去除硬掩模层，将替代间隔物沉积到伪栅极层上，在伪栅极层和替换间隔物上进行氧化物沉积，去除伪栅极和替换间隔物，从而在氧化物中形成栅极凹槽， 将栅极堆叠沉积到凹槽中。

公开(公告)号：US20120108024A1

公开(公告)日：2012-05-03

申请号：US13345252

申请日：2012-01-06

申请人： Josephine B. Chang ,  Michael A. Guillorn ,  Eric A. Joseph

发明人： Josephine B. Chang ,  Michael A. Guillorn ,  Eric A. Joseph

IPC分类号： H01L21/336 ,  B82Y40/00

CPC分类号： H01L51/001 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0541 ,  H01L51/0558

摘要： A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.

摘要翻译： 场效应晶体管（FET）包括由第一材料形成的漏极，由第一材料形成的源极，由将源极耦合到漏极的纳米结构形成的沟道以及在源极和漏极之间形成的栅极， 纳米结构。

公开(公告)号：US20120083123A1

公开(公告)日：2012-04-05

申请号：US13012836

申请日：2011-01-25

申请人： Josephine B. Chang ,  Leslie Charns ,  Jason E. Cummings ,  Michael A. Guillorn ,  Lukasz J. Hupka ,  Dinesh R. Koli ,  Tomohisa Konno ,  Mahadevaiyer Krishnan ,  Michael F. Lofaro ,  Jakub W. Nalaskowski ,  Masahiro Noda ,  Dinesh K. Penigalapati ,  Tatsuya Yamanaka

发明人： Josephine B. Chang ,  Leslie Charns ,  Jason E. Cummings ,  Michael A. Guillorn ,  Lukasz J. Hupka ,  Dinesh R. Koli ,  Tomohisa Konno ,  Mahadevaiyer Krishnan ,  Michael F. Lofaro ,  Jakub W. Nalaskowski ,  Masahiro Noda ,  Dinesh K. Penigalapati ,  Tatsuya Yamanaka

IPC分类号： H01L21/306

CPC分类号： H01L21/31053 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

摘要： A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.

摘要翻译： 平面化方法包括在第一化学机械抛光步骤中平坦化半导体晶片以去除覆盖层并平坦化顶层，从而在顶层之上留下厚度的顶层材料。 顶层材料在第二化学机械抛光步骤中被平坦化，以进一步去除顶层并暴露第二材料和第三材料的下层，使得顶层材料对第二材料对第三材料的选择性在 约1：1至约2：1：1，以提供平面形貌。

公开(公告)号：US08143113B2

公开(公告)日：2012-03-27

申请号：US12630939

申请日：2009-12-04

申请人： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

发明人： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC分类号： H01L21/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/26586 ,  H01L21/31111 ,  H01L21/31155 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

摘要： A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region.

摘要翻译： 一种形成纳米线隧道场效应晶体管器件的方法包括形成连接到第一焊盘区域和第二焊盘区域的纳米线，纳米线包括芯部分和电介质层，在纳米线的电介质层上形成栅极结构， 在所述纳米线的部分上形成第一保护隔离物，在所述暴露的纳米线和所述第一焊盘区域的第一部分中注入离子，将所述暴露的纳米线和所述第二焊盘区域的第二部分的电介质层注入， 从所述第二焊盘区域和所述第二部分去除所述暴露的纳米线的第二部分的芯部分以形成空腔，以及在所述空腔中外延生长掺杂半导体材料，以将所述纳米线的暴露的横截面与所述第二焊盘 地区。