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1.发明授权Chemical mechanical planarization processes for fabrication of FinFET devices 有权用于制造FinFET器件的化学机械平面化工艺公开(公告)号：US08513127B2
公开(公告)日：2013-08-20
申请号：US13012836
申请日：2011-01-25
申请人： Josephine B. Chang , Leslie Charns , Jason E. Cummings , Michael A. Guillorn , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
发明人： Josephine B. Chang , Leslie Charns , Jason E. Cummings , Michael A. Guillorn , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
IPC分类号： H01L21/302
CPC分类号： H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
摘要： A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.
摘要翻译： 平面化方法包括在第一化学机械抛光步骤中平坦化半导体晶片以去除覆盖层并平坦化顶层，从而在顶层之上留下厚度的顶层材料。 顶层材料在第二化学机械抛光步骤中被平坦化，以进一步去除顶层并暴露第二材料和第三材料的下层，使得顶层材料对第二材料对第三材料的选择性在 约1：1至约2：1：1，以提供平面形貌。
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2.发明申请Chemical Mechanical Planarization Processes For Fabrication of FINFET Devices 有权用于制造FINFET器件的化学机械平面化工艺公开(公告)号：US20120083123A1
公开(公告)日：2012-04-05
申请号：US13012836
申请日：2011-01-25
申请人： Josephine B. Chang , Leslie Charns , Jason E. Cummings , Michael A. Guillorn , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
发明人： Josephine B. Chang , Leslie Charns , Jason E. Cummings , Michael A. Guillorn , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
IPC分类号： H01L21/306
CPC分类号： H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
摘要： A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.
摘要翻译： 平面化方法包括在第一化学机械抛光步骤中平坦化半导体晶片以去除覆盖层并平坦化顶层，从而在顶层之上留下厚度的顶层材料。 顶层材料在第二化学机械抛光步骤中被平坦化，以进一步去除顶层并暴露第二材料和第三材料的下层，使得顶层材料对第二材料对第三材料的选择性在 约1：1至约2：1：1，以提供平面形貌。
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公开(公告)号：US09368502B2
公开(公告)日：2016-06-14
申请号：US13274758
申请日：2011-10-17
CPC分类号： H01L27/10867 , H01L21/845 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10861 , H01L27/10876 , H01L27/10879 , H01L27/1207 , H01L29/0673 , H01L29/49 , H01L29/66545 , H01L29/785
摘要： A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.
摘要翻译： 存储器单元，存储器单元阵列，以及用于制造具有诸如完全耗尽的finFET或嵌入式DRAM中的纳米线晶体管等多重晶体管的存储单元的方法。 存储单元包括沟槽电容器，非平面晶体管和将沟槽电容器电耦合到非平面晶体管的自对准硅化物互连。
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公开(公告)号：US09214529B2
公开(公告)日：2015-12-15
申请号：US13047132
申请日：2011-03-14
CPC分类号： H01L29/66545 , B82Y10/00 , H01L27/1211 , H01L29/66795 , H01L29/7855
摘要： A FinFET device with an independent control gate, including: a silicon-on-insulator substrate; a non-planar multi-gate transistor disposed on the silicon-on-insulator substrate, the transistor comprising a conducting channel wrapped around a thin silicon fin; a source/drain extension region; an independently addressable control gate that is self-aligned to the fin and does not extend beyond the source/drain extension region, the control gate comprising: a thin layer of silicon nitride; and a plurality of spacers.
摘要翻译： 一种具有独立控制栅极的FinFET器件，包括：绝缘体上硅衬底; 设置在绝缘体上硅衬底上的非平面多栅极晶体管，所述晶体管包括围绕薄硅片缠绕的导电沟道; 源极/漏极延伸区域; 独立可寻址的控制栅极，其与所述鳍片自对准并且不延伸超过所述源极/漏极延伸区域，所述控制栅极包括：氮化硅薄层; 和多个间隔件。
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公开(公告)号：US08492748B2
公开(公告)日：2013-07-23
申请号：US13169542
申请日：2011-06-27
CPC分类号： H01L29/66045 , H01L51/055
摘要： A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.
摘要翻译： 一次性材料层首先沉积在石墨烯层或碳纳米管（CNT）上。 一次性材料层包括比石墨烯或CNT更不惰性的材料，使得可以以目标电介质厚度沉积连续的电介质材料层而没有针孔。 通过图案化连续的介电材料层和沉积在其上的栅极导体层来形成栅极叠层。 一次性材料层在形成栅极叠层期间屏蔽并保护石墨烯层或CNT。 然后通过选择性蚀刻去除一次性材料层，释放独立的栅极结构。 独立栅极结构在选择性蚀刻结束时在石墨烯层或CNT上折叠，使得连续介电材料层的底表面接触石墨烯层或CNT的上表面。
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公开(公告)号：US20130092992A1
公开(公告)日：2013-04-18
申请号：US13274758
申请日：2011-10-17
IPC分类号： H01L27/108 , H01L21/02 , B82Y99/00
CPC分类号： H01L27/10867 , H01L21/845 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10861 , H01L27/10876 , H01L27/10879 , H01L27/1207 , H01L29/0673 , H01L29/49 , H01L29/66545 , H01L29/785
摘要： A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.
摘要翻译： 存储器单元，存储器单元阵列，以及用于制造具有诸如完全耗尽的finFET或嵌入式DRAM中的纳米线晶体管等多重晶体管的存储单元的方法。 存储单元包括沟槽电容器，非平面晶体管和将沟槽电容器电耦合到非平面晶体管的自对准硅化物互连。
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公开(公告)号：US20120302005A1
公开(公告)日：2012-11-29
申请号：US13566050
申请日：2012-08-03
申请人： Cyril Cabral, JR. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
发明人： Cyril Cabral, JR. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
IPC分类号： H01L21/336 , B82Y40/00
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/16 , H01L29/1602 , H01L51/0048 , H01L51/0541 , H01L51/105
摘要： A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.
摘要翻译： 场效应晶体管包括金属碳化物源部分，金属碳化物漏极部分，将金属碳化物源部分与金属碳化物部分分离的绝缘碳部分，形成在绝缘和碳部分上的纳米结构，并将金属碳化物源部分连接到 金属碳化物排出部分和形成在绝缘碳部分的至少一部分和至少一部分纳米结构上的栅堆叠。
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公开(公告)号：US07893492B2
公开(公告)日：2011-02-22
申请号：US12371943
申请日：2009-02-17
IPC分类号： H01L21/02
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66772 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696 , Y10S977/72 , Y10S977/742 , Y10S977/762 , Y10S977/938
摘要： A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.
摘要翻译： 提供一种半导体结构，其包括位于衬底表面上的多个垂直堆叠且垂直间隔开的半导体纳米线（例如，半导体纳米线网）。 每个垂直堆叠和垂直间隔开的半导体纳米线的一个端段连接到源极区域，并且每个垂直堆叠和垂直间隔开的半导体纳米线的另一个端部段连接到漏极区域。 包括栅极电介质和栅极导体的栅极区域邻接多个垂直堆叠和垂直间隔的半导体纳米线，并且源极区域和漏极区域与栅极区域自对准。
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公开(公告)号：US08816328B2
公开(公告)日：2014-08-26
申请号：US13617943
申请日：2012-09-14
IPC分类号： H01L29/06 , H01L31/00 , H01L29/76 , H01L21/02 , H01L21/84 , H01L21/336 , H01L51/00 , H01L29/775 , H01L29/423
CPC分类号： H01L51/0048 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L51/055 , H01L51/102 , Y10S977/742 , Y10S977/938
摘要： A method to fabricate a carbon nanotube (CNT)-based transistor includes providing a substrate having a CNT disposed over a surface; forming a protective electrically insulating layer over the CNT and forming a first multi-layer resist stack (MLRS) over the protective electrically insulating layer. The first MLRS includes a bottom layer, an intermediate layer and a top layer of resist. The method further includes patterning and selectively removing a portion of the first MLRS to define an opening for a gate stack while leaving the bottom layer; selectively removing a portion of the protective electrically insulating layer within the opening to expose a first portion of the CNT; forming the gate stack within the opening and upon the exposed first portion of the carbon nanotube, followed by formation of source and drain contacts also in accordance with the inventive method so as to expose second and third portions of the CNT.
摘要翻译： 制造基于碳纳米管（CNT）的晶体管的方法包括：提供具有设置在表面上的CNT的衬底; 在所述CNT上形成保护电绝缘层，并在所述保护电绝缘层上形成第一多层抗蚀剂叠层（MLRS）。 第一MLRS包括底层，中间层和顶层抗蚀剂。 该方法还包括图案化并选择性地移除第一MLRS的一部分以在离开底层的同时限定栅极堆叠的开口; 选择性地去除所述开口内的所述保护电绝缘层的一部分以暴露所述CNT的第一部分; 在开口内和在碳纳米管的暴露的第一部分之后形成栅极堆叠，随后根据本发明的方法形成源极和漏极接触，以暴露CNT的第二和第三部分。
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公开(公告)号：US08765613B2
公开(公告)日：2014-07-01
申请号：US13281688
申请日：2011-10-26
申请人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C. M. Fuller , Michael A. Guillorn , Masahiro Nakamura
发明人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C. M. Fuller , Michael A. Guillorn , Masahiro Nakamura
IPC分类号： H01L21/302
CPC分类号： H01L29/6653 , H01L21/31116 , H01L21/76802 , H01L21/76897 , H01L29/6656 , H01L29/6659
摘要： An anisotropic silicon nitride etch provides selectivity to silicon and silicon oxide by forming a fluorohydrocarbon-containing polymer on silicon surfaces and silicon oxide surfaces. Selective fluorohydrocarbon deposition is employed to provide selectivity to non-nitride surfaces. The fluorohydrocarbon-containing polymer interacts with silicon nitride to form a volatile compound, thereby enabling etching of silicon nitride. The fluorohydrocarbon-containing polymer interacts with silicon oxide at a low reaction rate, retarding, or completely stopping, the etching of silicon oxide. The fluorohydrocarbon-containing polymer does not interact with silicon, and protects silicon from the plasma. The anisotropic silicon nitride etch can be employed to etch silicon nitride selective to silicon and silicon oxide in any dimension, including small dimensions less than 50 nm.
摘要翻译： 各向异性氮化硅蚀刻通过在硅表面和氧化硅表面上形成含氟代烃的聚合物来提供对硅和氧化硅的选择性。 使用选择性氟代烃沉积来提供对非氮化物表面的选择性。 含氟烃聚合物与氮化硅相互作用以形成挥发性化合物，从而能够蚀刻氮化硅。 含氟烃聚合物以低反应速率与氧化硅相互作用，阻止或完全停止氧化硅的蚀刻。 含氟烃聚合物不与硅相互作用，并保护硅免受等离子体的影响。 可以采用各向异性氮化硅蚀刻来蚀刻任选尺寸的硅和氧化硅的氮化硅，包括小于50nm的小尺寸。
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