公开(公告)号：US20050282393A1

公开(公告)日：2005-12-22

申请号：US10710061

申请日：2004-06-16

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens

IPC分类号： H01L21/302 ,  H01L21/308 ,  H01L21/8242

CPC分类号： H01L21/3081 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/1087

摘要： A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench.

摘要翻译： 提供一种用于形成围绕半导体衬底中的沟槽的一部分的环的结构和方法，所述套环具有与邻近所述沟槽的下部设置的掩埋板的顶部边缘自对准的下边缘。

公开(公告)号：US20050151213A1

公开(公告)日：2005-07-14

申请号：US10707746

申请日：2004-01-08

申请人： Jon Casey ,  William Ferrante ,  Edward Kiewra ,  Carl Radens ,  William Tonti

发明人： Jon Casey ,  William Ferrante ,  Edward Kiewra ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/28 ,  G01K7/22 ,  H01C7/00 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L21/00 ,  H01L27/14 ,  H01L29/82 ,  H01L31/058

CPC分类号： H01L21/76895 ,  G01K7/226 ,  H01C7/006 ,  H01L21/76224 ,  H01L21/76838

摘要： A structure and method are provided for forming a thermistor. Isolation structures are formed in a substrate including at least an upper layer of a single crystal semiconductor. A layer of salicide precursor is deposited over the isolation region and the upper layer. The salicide precursor is then reacted with the upper layer to form a salicide self-aligned to the upper layer. Finally, the unreacted portions of the salicide precursor are then removed while preserving a portion of the salicide precursor over the isolation region as a body of the thermistor. An alternative integrated circuit thermistor is formed from a region of thermistor material in an embossed region of an interlevel dielectric (ILD).

摘要翻译： 提供了用于形成热敏电阻的结构和方法。 隔离结构形成在至少包括单晶半导体的上层的基板中。 一层自杀化合物前体沉积在隔离区和上层上。 然后将自对准硅化物前体与上层反应以形成与上层自对准的自对准硅化物。 最后，除去自对准硅胶前体的未反应部分，同时在作为热敏电阻体的隔离区域上保留一部分自杀化合物前体。 一种替代的集成电路热敏电阻由层间电介质（ILD）的压花区域中的热敏电阻材料的区域形成。

公开(公告)号：US20050128682A1

公开(公告)日：2005-06-16

申请号：US11043760

申请日：2005-01-26

申请人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Carl Radens ,  Keith Hon Wong ,  Chih-Chao Vang

发明人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Carl Radens ,  Keith Hon Wong ,  Chih-Chao Vang

IPC分类号： H01G4/255 ,  H01L21/02 ,  H01L21/66 ,  H01G4/06

CPC分类号： H01G4/255 ,  H01L22/22 ,  H01L28/40

摘要： A method and apparatus for adjusting capacitance of an on-chip capacitor uses exposure of a dielectric material of the capacitor to an ion beam comprising ions of at least one material to modify a dielectric constant of the dielectric material.

公开(公告)号：US20050070127A1

公开(公告)日：2005-03-31

申请号：US10674719

申请日：2003-09-30

申请人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Carl Radens ,  Keith Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Carl Radens ,  Keith Hon Wong ,  Chih-Chao Yang

IPC分类号： H01G4/255 ,  H01L21/02 ,  H01L21/66 ,  H01G4/35

CPC分类号： H01G4/255 ,  H01L22/22 ,  H01L28/40

摘要： A method and apparatus for adjusting capacitance of an on-chip capacitor uses exposure of a dielectric material of the capacitor to an ion beam comprising ions of at least one material to modify a dielectric constant of the dielectric material.

摘要翻译： 用于调整片上电容器的电容的方法和装置使用将电容器的电介质材料暴露于包含至少一种材料的离子的离子束，以改变介电材料的介电常数。

公开(公告)号：US06548358B2

公开(公告)日：2003-04-15

申请号：US09769494

申请日：2001-01-26

申请人： Kenneth C. Arndt ,  Dureseti Chidambarrao ,  Louis L. Hsu ,  Jack A. Mandelman ,  Carl Radens

发明人： Kenneth C. Arndt ,  Dureseti Chidambarrao ,  Louis L. Hsu ,  Jack A. Mandelman ,  Carl Radens

IPC分类号： H01L21336

CPC分类号： H01L23/62 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

摘要翻译： 半导体保险丝位于用于连接布线的导体之间。 保险丝包括位于相邻导体上的间隔物，以及定位在间隔件之间并连接到布线的熔丝元件。 导体之间的空间包括包含尽可能小的光刻宽度的第一宽度，并且熔丝元件具有小于第一宽度的第二宽度。

公开(公告)号：US06258689B1

公开(公告)日：2001-07-10

申请号：US09626328

申请日：2000-07-26

申请人： Gary B. Bronner ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Rick L. Mohler ,  Carl Radens ,  William R. Tonti

发明人： Gary B. Bronner ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Rick L. Mohler ,  Carl Radens ,  William R. Tonti

IPC分类号： H01L2120

CPC分类号： H01L27/10861 ,  H01L29/66181

摘要： Trench capacitors are fabricated utilizing a method which results in a metallic nitride as a portion of a node electrode in a lower region of the trench. The metallic nitride-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells having various trench configuration and design.

摘要翻译： 使用导致在沟槽的下部区域中作为节点电极的一部分的金属氮化物的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含金属氮化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元布局和/或降低的单元访问时间。 本发明的沟槽电容器特别可用作具有各种沟槽结构和设计的DRAM存储单元的组件。

公开(公告)号：US6013937A

公开(公告)日：2000-01-11

申请号：US938196

申请日：1997-09-26

申请人： Jochen Beintner ,  Ulrike Gruening ,  Carl Radens

发明人： Jochen Beintner ,  Ulrike Gruening ,  Carl Radens

IPC分类号： H01L21/76 ,  H01L21/308 ,  H01L21/31 ,  H01L21/316 ,  H01L21/318 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/00 ,  H01L21/336 ,  H01L21/469 ,  H01L29/06

CPC分类号： H01L27/1087 ,  H01L21/3081 ,  H01L21/31 ,  H01L21/763 ,  H01L27/10867 ,  Y10S438/97

摘要： A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.

摘要翻译： 设置在半导体衬底102上的衬垫层和布置在焊盘层内的缓冲层108，使得衬垫层被分为缓冲层下面的介电层106和缓冲层上方的掩模层110。 在半导体芯片上形成具有均匀平坦度和厚度的层的方法包括以下步骤：提供具有形成在其上的热垫106的衬底，在热衬垫上形成电介质层106，在电介质层上形成缓冲层108，其中， 缓冲层由与电介质层不同的材料制成，并在缓冲层上形成掩模层110，其中缓冲层由与掩模层不同的材料制成。

公开(公告)号：US08680577B2

公开(公告)日：2014-03-25

申请号：US13494965

申请日：2012-06-12

申请人： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

发明人： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

IPC分类号： H01L29/78

CPC分类号： H01L29/66666 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/7781

摘要： A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

摘要翻译： 一种半导体器件，其具有位于源极区域和漏极区域之间的与栅极电极的两侧相邻的凹部中的栅极。 沟道区域低于源极区域的大部分以及漏极区域和整个栅极电极的大部分。

公开(公告)号：US20120183743A1

公开(公告)日：2012-07-19

申请号：US13432036

申请日：2012-03-28

申请人： Timothy J. Dalton ,  Bruce B. Doris ,  Ho-Cheol Kim ,  Carl Radens

发明人： Timothy J. Dalton ,  Bruce B. Doris ,  Ho-Cheol Kim ,  Carl Radens

IPC分类号： B32B3/30

CPC分类号： H01L21/0337 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/0338 ,  Y10T428/24612

摘要： A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.

公开(公告)号：US20120183736A1

公开(公告)日：2012-07-19

申请号：US13430177

申请日：2012-03-26

申请人： Charles T. Black ,  Timothy J. Dalton ,  Bruce B. Doris ,  Carl Radens

发明人： Charles T. Black ,  Timothy J. Dalton ,  Bruce B. Doris ,  Carl Radens

IPC分类号： B32B3/10 ,  B32B3/30

CPC分类号： H01L21/0338 ,  B81B2203/0369 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  H01L21/0337 ,  H01L51/0017 ,  Y10S977/882 ,  Y10S977/887 ,  Y10S977/888 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24612 ,  Y10T428/24736 ,  Y10T428/24802

摘要： In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ⅓ of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.