公开(公告)号：US07217668B2

公开(公告)日：2007-05-15

申请号：US11013838

申请日：2004-12-16

申请人： Eugene A. Fitzgerald ,  Richard Hammond ,  Matthew Currie

发明人： Eugene A. Fitzgerald ,  Richard Hammond ,  Matthew Currie

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L21/336

CPC分类号： H01L29/66477 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28238 ,  H01L29/1054 ,  H01L29/78 ,  H01L29/7838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer, and a Si1-yGey layer; removing the Si1-yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.

摘要翻译： 一种制造半导体器件的方法，包括提供半导体异质结构，所述异质结构在衬底上具有松弛的Si 1-x Ge 2 x层，在弛豫时产生应变通道层 Si 1-x Ge Ge层，以及Si 1-y Ge Ge层; 除去Si 1-y Y y Y y层; 并提供介电层。 电介质层包括MISFET的栅极电介质。 在替代实施例中，异质结构包括SiGe间隔层和Si层。

公开(公告)号：US07081410B2

公开(公告)日：2006-07-25

申请号：US10826156

申请日：2004-04-16

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L21/302

CPC分类号： H01L21/02505 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  Y10S438/933

摘要： A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer. In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer.

公开(公告)号：US07074623B2

公开(公告)日：2006-07-11

申请号：US10456708

申请日：2003-06-06

申请人： Anthony J. Lochtefeld ,  Thomas A. Langdo ,  Richard Hammond ,  Matthew T. Currie ,  Glyn Braithwaite ,  Eugene A. Fitzgerald

发明人： Anthony J. Lochtefeld ,  Thomas A. Langdo ,  Richard Hammond ,  Matthew T. Currie ,  Glyn Braithwaite ,  Eugene A. Fitzgerald

IPC分类号： H01L21/335 ,  H01L21/00 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/76254 ,  H01L21/76259 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66916 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78684 ,  H01L29/78687

摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

摘要翻译： 应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

公开(公告)号：US06974735B2

公开(公告)日：2005-12-13

申请号：US10216085

申请日：2002-08-09

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L21/8238 ,  H01L29/10 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L29/1054 ,  Y10S438/933

摘要： A semiconductor-based device includes a channel layer, which includes a distal layer and a proximal layer in contact with the distal layer. The distal layer supports at least a portion of hole conduction for at least one p-channel component, and the proximal layer supports at least a portion of electron conduction for at least one n-channel component. The proximal layer has a thickness that permits a hole wave function to effectively extend from the proximal layer into the distal layer to facilitate hole conduction by the distal layer. A method for fabricating a semiconductor-based device includes providing a distal portion of a channel layer and providing a proximal portion of the channel layer.

摘要翻译： 基于半导体的器件包括沟道层，其包括远端层和与远端层接触的近端层。 远端层支撑至少一个p沟道分量的至少一部分空穴传导，并且近端支撑至少一个n沟道分量的至少一部分电子传导。 近端层具有允许空穴波函数从近端层有效地延伸到远侧层中的厚度，以便于远端层的空穴传导。 一种用于制造基于半导体的器件的方法包括提供沟道层的远端部分并提供沟道层的近端部分。

公开(公告)号：US06927147B2

公开(公告)日：2005-08-09

申请号：US10603850

申请日：2003-06-25

申请人： Eugene A. Fitzgerald ,  Arthuer J. Pitera

发明人： Eugene A. Fitzgerald ,  Arthuer J. Pitera

IPC分类号： H01L21/20 ,  H01L21/762 ,  H01L21/30

CPC分类号： H01L21/76254 ,  H01L21/2007 ,  H01L21/76256 ,  Y10T428/25

摘要： A method of bonding lattice-mismatched semiconductors is provided. The method includes forming a Ge-based virtual substrate and depositing on the virtual substrate a CMP layer that forms a planarized virtual substrate. Also, the method includes bonding a Si substrate to the planarized virtual substrate and performing layer exfoliation on selective layers of the planarized virtual substrate producing a damaged layer of Ge. Furthermore, the method includes removing the damaged layer of Ge.

摘要翻译： 提供了结合晶格失配的半导体的方法。 该方法包括形成Ge基虚拟衬底并在虚拟衬底上沉积形成平坦化虚拟衬底的CMP层。 此外，该方法包括将Si衬底接合到平坦化虚拟衬底并且在平坦化的虚拟衬底的选择层上进行层剥离，产生损伤的Ge层。 此外，该方法包括去除损坏的Ge层。

公开(公告)号：US06876010B1

公开(公告)日：2005-04-05

申请号：US09611024

申请日：2000-07-06

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L21/20 ,  H01L31/072

CPC分类号： H01L21/02505 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  Y10S438/933

摘要： A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer. In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer.

摘要翻译： 一种半导体结构，包括半导体衬底，在衬底上的至少一个第一晶体外延层，第一层具有被平坦化的表面，以及在至少一个第一层上的至少一个第二晶体外延层。 在本发明的另一个实施例中，提供了包括硅衬底和在硅衬底上生长的GeSi分级区域的半导体结构，压缩应变被并入渐变区域以抵消在热处理期间结合的拉伸应变。 在本发明的另一个实施例中，提供了一种半导体结构，其包括半导体衬底，具有在衬底上生长的渐变区域的第一层，压缩应变结合在渐变区域中以抵消在热处理期间结合的拉伸应变， 所述第一层具有平坦化的表面，以及设置在所述第一层上的第二层。 在本发明的另一个实施例中，提供了一种制造半导体结构的方法，包括提供半导体衬底，在衬底上提供至少一个第一晶体外延层，并平坦化第一层的表面。

公开(公告)号：US06805744B2

公开(公告)日：2004-10-19

申请号：US10023047

申请日：2001-12-13

申请人： Andrew Y. Kim ,  Eugene A. Fitzgerald

发明人： Andrew Y. Kim ,  Eugene A. Fitzgerald

IPC分类号： C30B2506

CPC分类号： H01L21/02392 ,  C30B25/02 ,  C30B29/40 ,  H01L21/02395 ,  H01L21/02461 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02543 ,  H01L21/02576 ,  H01L21/0262 ,  H01L31/1844 ,  H01L33/0062 ,  H01L33/0066 ,  H01L33/30 ,  Y02E10/544

摘要： A method of forming a semiconductor structure including providing a single crystal semiconductor substrate of GaP, and fabricating a graded composition buffer including a plurality of epitaxial semiconductor Inx(AlyGa1−y)1−xP alloy layers. The buffer includes a first alloy layer immediately contacting the substrate having a lattice constant that is nearly identical to that of the substrate, subsequent alloy layers having lattice constants that differ from adjacent layers by less than 1%, and a final alloy layer having a lattice constant that is substantially different from the substrate. The growth temperature of the final alloy layer is at least 20° C. less than the growth temperature of the first alloy layer.

摘要翻译： 一种形成半导体结构的方法，包括提供GaP的单晶半导体衬底，以及制造包括多个外延半导体In x（Al y Ga 1-y）1-xP合金层的渐变组合物缓冲层。 缓冲器包括立即接触基板的第一合金层，其具有与基板的晶格常数几乎相同的晶格常数，随后的合金层具有不同于相邻层的晶格常数小于1％，以及具有晶格的最终合金层 基本上不同于基底的常数。 最终合金层的生长温度比第一合金层的生长温度低至少20℃。

公开(公告)号：US06737670B2

公开(公告)日：2004-05-18

申请号：US10384160

申请日：2003-03-07

申请人： Zhi-Yuan Cheng ,  Eugene A. Fitzgerald ,  Dimitri A. Antoniadis ,  Judy L. Hoyt

发明人： Zhi-Yuan Cheng ,  Eugene A. Fitzgerald ,  Dimitri A. Antoniadis ,  Judy L. Hoyt

IPC分类号： H01L2906

CPC分类号： H01L21/76254 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02546 ,  Y10S438/933

摘要： A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1−xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1−yGey layer, a thin strained Si1−zGez layer and another relaxed Si1−yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1−yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1−yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1−xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth. The relaxed GaAs layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the hydrogen ion rich layer, such that the upper portion of relaxed GaAs layer remains on the second substrate.

公开(公告)号：US06583015B2

公开(公告)日：2003-06-24

申请号：US09923207

申请日：2001-08-06

申请人： Eugene A. Fitzgerald ,  Richard Hammond ,  Matthew Currie

发明人： Eugene A. Fitzgerald ,  Richard Hammond ,  Matthew Currie

IPC分类号： H01L21336

CPC分类号： H01L29/66477 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28238 ,  H01L29/1054 ,  H01L29/78 ,  H01L29/7838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1−xGex layer on a substrate, a strained channel layer on the relaxed Si1−xGex layer, and a Si1−yGey layer; removing the Si1−yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.

公开(公告)号：US08822282B2

公开(公告)日：2014-09-02

申请号：US10854556

申请日：2004-05-26

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L29/72

CPC分类号： H01L29/802 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/76251 ,  H01L21/76256 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66893 ,  H01L29/66916 ,  H01L29/78 ,  H01L29/7838

摘要： Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

摘要翻译： 使用平面弛豫SiGe作为材料平台制造高速数字，模拟和组合数字/模拟系统的结构和方法。 松弛的SiGe允许具有增强的电子特性的大量应变Si层。 通过允许MOSFET通道处于表面或掩埋，可以创建高速数字和/或模拟电路。 在沉积器件外延层之前的平坦化确保了用于最先进光刻的平坦表面。