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公开(公告)号：US20130122686A1
公开(公告)日：2013-05-16
申请号：US13298112
申请日：2011-11-16
IPC分类号： H01L21/762 , H01L21/20
CPC分类号： H01L21/02653 , H01L21/02639 , H01L21/0337 , H01L21/76224 , H01L21/76229
摘要： A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches.
摘要翻译： 一种方法包括在衬底上形成硬掩模，图案化硬掩模以形成第一多个沟槽，以及将电介质材料填充到第一多个沟槽中以形成多个电介质区域。 硬掩模从多个电介质区域之间移除，其中第二多个沟槽被去除的硬掩模留下。 进行外延步骤以在第二多个沟槽中生长半导体材料。
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82.发明申请FINFET DEVICE HAVING A CHANNEL DEFINED IN A DIAMOND-LIKE SHAPE SEMICONDUCTOR STRUCTURE 有权具有金刚石形状半导体结构定义的通道的FINFET器件公开(公告)号：US20130049068A1
公开(公告)日：2013-02-28
申请号：US13220979
申请日：2011-08-30
IPC分类号： H01L29/772 , H01L21/20
CPC分类号： H01L29/66795 , H01L21/02532 , H01L21/02609 , H01L21/30604 , H01L21/76224 , H01L29/045 , H01L29/0649 , H01L29/0847 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/7853
摘要： The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.
摘要翻译： 本公开提供了一种FinFET器件。 FinFET器件包括第一半导体材料的半导体衬底; 覆盖半导体衬底的第一半导体材料的鳍结构，其中鳍结构具有第一晶面取向的顶表面; 设置在所述翅片结构的顶表面上的第二半导体材料的菱形形状结构，其中所述菱形形状结构具有至少一个第二晶面取向的表面; 设置在所述菱形形状结构上的栅极结构，其中所述栅极结构分离源极区域和漏极区域; 以及在源极和漏极区域之间以菱形形状结构限定的沟道区域。
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公开(公告)号：US20130001591A1
公开(公告)日：2013-01-03
申请号：US13174170
申请日：2011-06-30
IPC分类号： H01L29/78 , H01L21/336 , H01L29/24 , H01L29/26
CPC分类号： H01L21/823821 , H01L27/0924 , H01L29/1054 , H01L29/785
摘要： An integrated circuit device and method for manufacturing the same are disclosed. An exemplary device includes a semiconductor substrate having a substrate surface and a trench isolation structure disposed in the semiconductor substrate for isolating an NMOS region of the device and from a PMOS region of the device. The device further includes a first fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant greater than that of Ge; a second fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant smaller than that of Ge; and a gate structure disposed over and arranged perpendicular to the first and second fin structures.
摘要翻译： 公开了一种集成电路器件及其制造方法。 示例性器件包括具有衬底表面的半导体衬底和设置在半导体衬底中的用于隔离器件的NMOS区域和器件的PMOS区域的沟槽隔离结构。 该器件还包括第一鳍结构，其包括设置在具有高带隙能量和晶格常数大于Ge的III-V半导体材料的层上的硅或SiGe; 包括硅或SiGe的第二鳍结构，其设置在具有高带隙能量和比Ge小的晶格常数的III-V半导体材料层上; 以及设置在垂直于第一和第二鳍结构并且布置在其上的栅极结构。
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公开(公告)号：US08253167B2
公开(公告)日：2012-08-28
申请号：US12694002
申请日：2010-01-26
申请人： Heng-Kuang Lin , Pei-Chin Chiu , Jen-Inn Chyi , Han-Chieh Ho , Clement Hsingjen Wann , Chih-Hsin Ko , Cheng-Hsien Wu
发明人： Heng-Kuang Lin , Pei-Chin Chiu , Jen-Inn Chyi , Han-Chieh Ho , Clement Hsingjen Wann , Chih-Hsin Ko , Cheng-Hsien Wu
IPC分类号： H01L27/092
CPC分类号： H01L29/205 , B82Y10/00 , H01L21/8252 , H01L27/085 , H01L27/0883 , H01L27/092 , H01L29/122 , H01L29/42316 , H01L29/42356 , H01L29/66462 , H01L29/7783
摘要： An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.
摘要翻译： 集成电路结构包括基板和第一和第二多个III-V半导体层。 所述第一多个III-V半导体层包括在所述衬底上的第一底部阻挡层; 在第一底部屏障上的第一通道层; 以及第一通道层上的第一顶部势垒。 第一场效应晶体管（FET）包括第一沟道区，其包括第一沟道层的一部分。 第二多个III-V半导体层在第一多个III-V半导体层之上，并且包括第二底部屏障; 在第二底部屏障上的第二通道层; 以及在第二通道层上的第二顶部阻挡层。 第二FET包括第二沟道区，其包括第二沟道层的一部分。
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公开(公告)号：US20120028477A1
公开(公告)日：2012-02-02
申请号：US13268191
申请日：2011-10-07
IPC分类号： H01L21/312
CPC分类号： H01L21/0337 , H01L21/31144 , H01L21/76816
摘要： A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature.
摘要翻译： 提供一种制造半导体器件的方法，其包括提供衬底。 材料层形成在衬底上。 聚合物层形成在材料层上。 使用聚合物层的一部分自组装纳米尺寸的特征。 使用纳米尺寸的特征对衬底进行图案化。
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86.发明申请公开(公告)号：US20110306179A1
公开(公告)日：2011-12-15
申请号：US12814088
申请日：2010-06-11
CPC分类号： H01L21/0262 , C30B25/105 , C30B25/186 , C30B29/40 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02538 , H01L21/02639 , H01L21/76224
摘要： A device includes providing a silicon substrate; annealing the silicon substrate at a first temperature higher than about 900° C.; and lowering a temperature of the silicon substrate from the first temperature to a second temperature. A temperature lowering rate during the step of lowering the temperature is greater than about 1° C./second. A III-V compound semiconductor region is epitaxially grown on a surface of the silicon substrate using metal organic chemical vapor deposition (MOCVD).
摘要翻译： 一种器件包括提供硅衬底; 在高于约900℃的第一温度下退火硅衬底; 以及将所述硅衬底的温度从所述第一温度降低到第二温度。 在降低温度的步骤期间的降温速率大于约1℃/秒。 使用金属有机化学气相沉积（MOCVD）在硅衬底的表面上外延生长III-V族化合物半导体区域。
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公开(公告)号：US20110054658A1
公开(公告)日：2011-03-03
申请号：US12828591
申请日：2010-07-01
IPC分类号： G06F19/00
CPC分类号： G06F17/5068
摘要： A method for constant power density scaling in MOSFETs is provided. A method for manufacturing an integrated circuit includes computing fixed scaling factors for a first fabrication process based on a second fabrication process, computing settable scaling factors for the integrated circuit to be fabricated using the first fabrication process, determining parameters of the integrated circuit based on the settable scaling factors, and manufacturing the integrated circuit using the determined parameters. The first fabrication process creates devices having a smaller device dimension than the second fabrication process and the settable scaling factors are set based on the fixed scaling factors.
摘要翻译： 提供了一种用于MOSFET中恒定功率密度缩放的方法。 一种用于制造集成电路的方法包括：基于第二制造工艺计算用于第一制造工艺的固定缩放因子，使用第一制造工艺计算待制造的集成电路的可设定缩放因子，基于 可设置的缩放因子，并使用确定的参数制造集成电路。 第一制造工艺产生具有比第二制造工艺更小的装置尺寸的装置，并且可固定缩放因子基于固定缩放因子设定。
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公开(公告)号：US09601594B2
公开(公告)日：2017-03-21
申请号：US13295178
申请日：2011-11-14
CPC分类号： H01L29/0847 , H01L21/76224 , H01L29/66575 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor crystal material. The trench liner directly abuts the source/drain stressor device. The semiconductor device also includes a dielectric trench component that is disposed on the trench liner and filling the recess. The semiconductor device includes a source/drain stressor device that is disposed in the substrate. The source/drain stressor device is disposed between the gate and the trench liner.
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公开(公告)号：US09589803B2
公开(公告)日：2017-03-07
申请号：US13572494
申请日：2012-08-10
IPC分类号： H01L29/94 , H01L21/28 , H01L21/3105 , H01L29/66 , H01L21/8238 , H01L29/78 , H01L29/165
CPC分类号： H01L29/66545 , H01L21/28123 , H01L21/31053 , H01L21/3212 , H01L21/32134 , H01L21/32135 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface.
摘要翻译： 该描述涉及场效应晶体管的栅电极。 场效应晶体管的示例性结构包括：衬底; 位于所述基板上方的包括第一顶表面和侧壁的栅电极; 至少部分地设置在所述栅电极的一侧的所述衬底中的源极/漏极（S / D）区域; 在所述侧壁上的间隔物分布在所述栅电极和所述S / D区之间; 以及与所述间隔物相邻的接触蚀刻停止层（CESL），并且还包括在所述S / D区域上延伸的部分，其中所述部分具有与所述第一顶表面基本上共面的第二顶表面。
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90.发明授权Strained structure of semiconductor device and method of making the strained structure 有权半导体器件的应变结构和制造应变结构的方法公开(公告)号：US09171929B2
公开(公告)日：2015-10-27
申请号：US13487860
申请日：2012-06-04
IPC分类号： H01L29/78 , H01L27/092 , H01L29/66 , H01L29/10 , H01L29/165 , H01L21/8238 , H01L21/02
CPC分类号： H01L29/66636 , H01L21/02529 , H01L21/02532 , H01L21/02538 , H01L21/0262 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0924 , H01L29/1054 , H01L29/165 , H01L29/66651 , H01L29/7848
摘要： An exemplary structure for a field effect transistor (FET) comprises a silicon substrate comprising a first surface; a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, and a length parallel to first surface; and two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material.
摘要翻译： 用于场效应晶体管（FET）的示例性结构包括：硅衬底，其包括第一表面; 在所述第一表面上的通道部分，其中所述通道部分具有在所述第一表面上方的第一高度处的第二表面和平行于第一表面的长度; 以及沿沟道部分的长度围绕沟道部分的两个源极/漏极（S / D）区域，其中两个S / D区域包括SiGe，Ge，Si，SiC，GeSn，SiGeSn，SiSn， 或III-V材料。
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