公开(公告)号：US5295161A

公开(公告)日：1994-03-15

申请号：US698626

申请日：1991-05-10

申请人： Daniel M. Dreps ,  Raymond P. Rizzo

发明人： Daniel M. Dreps ,  Raymond P. Rizzo

IPC分类号： H03F3/34 ,  H03F3/08 ,  H03F3/45 ,  H04B10/158 ,  H04L25/06

CPC分类号： H04B10/6933 ,  H03F3/08

摘要： A differential transimpedance amplifier used in amplifying optical signals transmitted with a balanced code has a level restore circuit which integrates the digital output of the amplifier and feeds back the result to one of the differential inputs of the amplifier. The feedback signal removes imbalances from the amplifier output. The balanced amplifier output can then be processed by a clock reconstruction circuit to accurately sample the received optical signal with a low bit error rate.

摘要翻译： 用于放大用平衡码发射的光信号的差分跨阻放大器具有电平恢复电路，其对放大器的数字输出进行积分并将结果反馈到放大器的差分输入之一。 反馈信号消除了放大器输出的不平衡。 然后，平衡放大器输出可以由时钟重构电路处理，以以低误码率对接收的光信号进行精确采样。

公开(公告)号：US08543753B2

公开(公告)日：2013-09-24

申请号：US13080799

申请日：2011-04-06

申请人： Daniel M. Dreps ,  Kyu-hyoun Kim ,  Michael A. Sorna ,  Glen A. Wiedemeier

发明人： Daniel M. Dreps ,  Kyu-hyoun Kim ,  Michael A. Sorna ,  Glen A. Wiedemeier

IPC分类号： G06F1/10 ,  G06F13/38

CPC分类号： G06F13/385 ,  G06F1/10 ,  G06F13/4072 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1093

摘要： A multi-use physical (PHY) architecture that includes a PHY connection that includes one or more bit lines and that is communicatively coupled to a first processor. The PHY connection is configurable to carry signals between the first processor and a second processor, or between the first processor and a memory. The one or more bit lines are configured to carry signals bi-directionally at a first voltage when the PHY connection is configured to carry signals between the first processor and the memory. The one or more bit lines are configured to carry signals uni-directionally at a second voltage when the PHY connection is configured to carry signals between the first processor and the second processor. The second voltage is different than the first voltage.

摘要翻译： 一种多用途物理（PHY）架构，其包括包括一个或多个位线并且通信地耦合到第一处理器的PHY连接。 PHY连接可配置为在第一处理器和第二处理器之间或第一处理器和存储器之间传送信号。 一个或多个位线被配置为当PHY连接被配置为在第一处理器和存储器之间传送信号时以双向方式携带信号处于第一电压。 当PHY连接被配置为在第一处理器和第二处理器之间传送信号时，一个或多个位线被配置为以第二电压单向地传送信号。 第二电压不同于第一电压。

公开(公告)号：US08493801B2

公开(公告)日：2013-07-23

申请号：US13570430

申请日：2012-08-09

申请人： Daniel M. Dreps ,  Kevin C. Gower ,  Michael K. Kerr ,  Kyu-hyoun Kim ,  David W. Mann ,  James A. Mossman ,  Michael A. Sorna ,  Robert B. Tremaine ,  William M. Zevin

发明人： Daniel M. Dreps ,  Kevin C. Gower ,  Michael K. Kerr ,  Kyu-hyoun Kim ,  David W. Mann ,  James A. Mossman ,  Michael A. Sorna ,  Robert B. Tremaine ,  William M. Zevin

IPC分类号： G11C7/00

CPC分类号： G06F13/4243 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C2207/2254

摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.

摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。

公开(公告)号：US20120300564A1

公开(公告)日：2012-11-29

申请号：US13570430

申请日：2012-08-09

申请人： Daniel M. Dreps ,  Kevin C. Gower ,  Michael K. Kerr ,  Kyu-hyoun Kim ,  David W. Mann ,  James A. Mossman ,  Michael A. Sorna ,  Robert B. Tremaine ,  William M. Zevin

发明人： Daniel M. Dreps ,  Kevin C. Gower ,  Michael K. Kerr ,  Kyu-hyoun Kim ,  David W. Mann ,  James A. Mossman ,  Michael A. Sorna ,  Robert B. Tremaine ,  William M. Zevin

IPC分类号： G11C7/00

CPC分类号： G06F13/4243 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C2207/2254

摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.

摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。

公开(公告)号：US20120300563A1

公开(公告)日：2012-11-29

申请号：US13567353

申请日：2012-08-06

申请人： Kyu-Hyoun Kim ,  George L. Chiu ,  Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Warren E. Maule

发明人： Kyu-Hyoun Kim ,  George L. Chiu ,  Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Warren E. Maule

IPC分类号： G11C7/00

CPC分类号： G11C7/1078 ,  G06F11/1028 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

摘要翻译： 具有改进性能，降低功耗和增加可靠性的高级内存。 存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路 对错误控制编码电路检测接收到的命令中的错误。 另一个存储器件包括可编程序序。 另一存储器件包括快速退出自刷新模式。 另一种存储装置包括由特征装置控制的自动刷新功能。 另一存储器件包括由存储器件的特性控制的自动刷新功能。

公开(公告)号：US20120120577A1

公开(公告)日：2012-05-17

申请号：US12946328

申请日：2010-11-15

申请人： Sungjun Chun ,  Daniel M. Dreps ,  Dierk Kaller ,  Rohan U. Mandrekar ,  Lei Shan

发明人： Sungjun Chun ,  Daniel M. Dreps ,  Dierk Kaller ,  Rohan U. Mandrekar ,  Lei Shan

IPC分类号： G06F1/16

CPC分类号： G06F1/185 ,  G06F1/10

摘要： A memory module configured to connect to a slot of a data processing system. A set of tabs is connected to the module and configured to electrically connect the module to the slot and to electrically connect the module to a clock of the data processing system. The set of tabs includes a first tab, a second tab, a third tab, and a fourth tab. The first tab and the second tab are opposite the third tab and the fourth tab. The first tab comprises a positive type tab, the second tab comprises a negative type tab, the third tab comprises a positive type tab, and the fourth tab comprises a negative type tab. The first and third tabs are configured to provide a first electrical connection to the clock. The second and fourth tabs are configured to provide a second electrical connection to the clock. Together, the first, second, third, and fourth tabs comprise two dual tabs.

摘要翻译： 配置为连接到数据处理系统的时隙的存储器模块。 一组标签连接到模块并且被配置为将模块电连接到插槽并且将模块电连接到数据处理系统的时钟。 该组标签包括第一标签，第二标签，第三标签和第四标签。 第一个选项卡和第二个选项卡与第三个选项卡和第四个选项卡相对。 第一标签包括一个正型标签，该第二标签包括一个负型标签，该第三标签包括一个正型标签，该第四标签包括一个负型标签。 第一和第三选项卡被配置为提供到时钟的第一电连接。 第二和第四选项卡被配置为提供与时钟的第二电连接。 一起，第一，第二，第三和第四标签包括两个双标签。

公开(公告)号：US20100122107A1

公开(公告)日：2010-05-13

申请号：US12270576

申请日：2008-11-13

申请人： Ravi K. Arimilli ,  Daniel M. Dreps ,  Edward J. Seminaro

发明人： Ravi K. Arimilli ,  Daniel M. Dreps ,  Edward J. Seminaro

IPC分类号： G06F1/08 ,  G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4072 ,  G06F2213/0026 ,  G06F2213/0028 ,  Y02D10/14 ,  Y02D10/151

摘要： An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage.

摘要翻译： 集成处理器设计包括支持异质电气特性的物理接口宏。 处理器设计包括多个处理核心和多个物理接口以连接到存储器接口，用于输入/输出的外围组件互连快速（PCI Express或PCIe）接口，用于网络通信的以太网接口和/或 串行连接SCSI（SAS）接口进行存储。

公开(公告)号：US20100013454A1

公开(公告)日：2010-01-21

申请号：US12175555

申请日：2008-07-18

申请人： Daniel M. Dreps

发明人： Daniel M. Dreps

IPC分类号： H03H1/00

CPC分类号： G11C29/02 ,  G11C5/04 ,  G11C5/063 ,  G11C5/147 ,  G11C8/08 ,  G11C29/021 ,  G11C29/028

摘要： A voltage reference driver includes a voltage divider circuit with a voltage reference output node to output a voltage between a first voltage and a second voltage. The voltage reference driver also includes a first selectable impedance circuit coupled to a node at the first voltage and further coupled to the voltage reference output node, and a second selectable impedance circuit coupled to a node at the second voltage and further coupled to the voltage reference output node. Combinations of the first selectable impedance circuit and the second selectable impedance circuit are selectable such that a constant impedance is maintained at the voltage reference output node within a threshold value.

摘要翻译： 电压参考驱动器包括具有电压参考输出节点的分压器电路，以输出第一电压和第二电压之间的电压。 电压参考驱动器还包括耦合到处于第一电压的节点的第一可选择阻抗电路并进一步耦合到电压参考输出节点，以及第二可选阻抗电路，耦合到处于第二电压的节点，并且还耦合到电压基准 输出节点。 可选择第一可选择阻抗电路和第二可选择阻抗电路的组合，使得在阈值内的电压参考输出节点处保持恒定的阻抗。

公开(公告)号：US07242249B2

公开(公告)日：2007-07-10

申请号：US11055806

申请日：2005-02-11

申请人： Daniel M. Dreps ,  Bao G. Truong ,  Glen A. Wiedemeier

发明人： Daniel M. Dreps ,  Bao G. Truong ,  Glen A. Wiedemeier

IPC分类号： H03F3/45 ,  H03K19/094

CPC分类号： G11C7/1078 ,  G11C7/02 ,  G11C7/1084

摘要： A receiver circuit is configured as a frequency compensated differential amplifier having one input coupled to the output of a transmission line to receive a transmitted signal and the second input coupled to a reference voltage. The differential amplifier has a high frequency gain equivalent to the gain of an uncompensated differential stage for the transmitted signal. The compensated differential amplifier has an attenuated low frequency gain for signal frequencies substantially lower than the high frequency and a transitional gain for frequencies between the low and high frequencies. A compensated stage provides the portion of the signal with a compensated response and an uncompensated stage provides the portion of the amplified signal that is uncompensated. Bias control signals determine how much of the output signal is from the compensated and uncompensated stages as a means for customizing response from transmission lines with varying losses.

摘要翻译： 接收器电路被配置为频率补偿差分放大器，其具有耦合到传输线的输出的一个输入以接收传输的信号，而第二输入耦合到参考电压。 差分放大器具有等于发射信号的未补偿差分级的增益的高频增益。 补偿的差分放大器对于低于高频的信号频率具有衰减的低频增益，对于低频和高频之间的频率具有过渡增益。 补偿级为信号的一部分提供补偿响应，并且未补偿级提供未被补偿的放大信号的部分。 偏置控制信号确定来自补偿和无补偿级的输出信号的大小是用于定制来自具有不同损耗的传输线的响应的手段。

公开(公告)号：US5604466A

公开(公告)日：1997-02-18

申请号：US345280

申请日：1994-11-28

申请人： Daniel M. Dreps ,  Raymond P. Rizzo

发明人： Daniel M. Dreps ,  Raymond P. Rizzo

IPC分类号： H03K3/282 ,  H03L7/099 ,  H03L7/14 ,  H03K3/281

CPC分类号： H03K3/2821 ,  H03L7/099 ,  H03L7/14 ,  Y10S323/907

摘要： An on-chip voltage controlled oscillator for use in an analog phase locked loop receives power from a voltage regulator which greatly reduces the noise seen by the voltage controlled oscillator. The voltage controlled oscillator has a DC bias section which supplies a relatively constant current to the multivibrator to assure a minimum operating frequency. A control signal is used to provide additional current which increases the speed of oscillation. The bias current reduces the transfer characteristics (MHz/volt) of the voltage controlled oscillator making it more immune to noise in the control signal.

摘要翻译： 用于模拟锁相环的片上压控振荡器从电压调节器接收电力，这大大降低了压控振荡器所看到的噪声。 压控振荡器具有DC偏压部分，其向多谐振荡器提供相对恒定的电流以确保最小工作频率。 控制信号用于提供增加振荡速度的附加电流。 偏置电流降低了压控振荡器的传输特性（MHz /伏特），使其更加免于控制信号中的噪声。