公开(公告)号：US20150206754A1

公开(公告)日：2015-07-23

申请号：US14161724

申请日：2014-01-23

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： David V. Horak ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/28 ,  H01L29/423

CPC classification number: H01L29/0653 ,  H01L21/28008 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.

Abstract translation: 形成半导体结构的方法包括在半导体衬底上形成具有第一导电材料的栅极结构，在第一导电材料的相对侧上的栅极间隔物和围绕栅极间隔物的第一层间电介质（ILD）层和第一导电 材料。 第一导电材料的上部是凹进的。 栅极间隔物凹进直到栅极间隔物的高度小于栅极结构的高度。 隔离衬垫沉积在栅极间隔物和第一导电材料上方。 去除隔离衬垫的一部分，使得第一导电材料的顶表面露出。 第二导电材料沉积在形成在第一导电材料和栅极间隔物上方的接触孔中以形成栅极接触。

公开(公告)号：US08937359B2

公开(公告)日：2015-01-20

申请号：US13894513

申请日：2013-05-15

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Shom Ponoth ,  David V. Horak ,  Balasubramanian Pranatharthiharan

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66666

Abstract: Embodiments of the invention provide approaches for forming gate and source/drain (S/D) contacts. Specifically, the semiconductor device includes a gate transistor formed over a substrate, a S/D contact formed over a trench-silicide (TS) layer and positioned adjacent the gate transistor, and a gate contact formed over the gate transistor, wherein at least a portion of the gate contact is aligned over the TS layer. This structure enables contact with the TS layer, thereby decreasing the distance between the gate contact and the source/drain, which is desirable for ultra-area-scaling.

Abstract translation: 本发明的实施例提供了用于形成栅极和源极/漏极（S / D）触点的方法。 具体地，半导体器件包括形成在衬底上的栅极晶体管，形成在沟槽硅化物（TS）层上并且邻近栅极晶体管定位的S / D接触，以及形成在栅极晶体管上的栅极接触，其中至少一个 栅极触点的一部分在TS层上对齐。 这种结构使得能够与TS层接触，从而减小栅极接触和源极/漏极之间的距离，这对于超区域缩放是期望的。

公开(公告)号：US20140264486A1

公开(公告)日：2014-09-18

申请号：US13839626

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/4232 ,  H01L21/28247 ,  H01L29/66545 ,  H01L29/78

Abstract: One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving a portion of the gate cap protection layer positioned on the upper surface of the gate cap layer. A device disclosed herein includes a gate/spacer structure positioned in a layer of insulating material, a gate cap layer positioned on the gate/spacer structure, wherein sidewalls of the gate cap layer contact the layer of insulating material, and a gate cap protection layer positioned on an upper surface of the gate cap layer, wherein the sidewalls of the gate cap protection layer also contact the layer of insulating material.

Abstract translation: 一种方法包括形成凹入的栅极/间隔结构，其部分地限定间隔物/栅极盖凹部，在间隔物/栅极盖凹部中形成栅极盖层，在栅极盖层的上表面上形成栅极盖保护层，以及 去除栅极帽保护层的部分，留下栅极盖保护层的一部分位于栅极盖层的上表面上。 本文公开的装置包括定位在绝缘材料层中的栅极/间隔结构，位于栅极/间隔物结构上的栅极盖层，其中栅极盖层的侧壁接触绝缘材料层，栅极盖保护层 定位在栅极盖层的上表面上，其中栅极盖保护层的侧壁也接触绝缘材料层。

公开(公告)号：US10818773B2

公开(公告)日：2020-10-27

申请号：US15276060

申请日：2016-09-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/283 ,  H01L27/088 ,  H01L29/417 ,  H01L23/485 ,  H01L29/78 ,  H01L23/532 ,  H01L23/535 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/08

Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.

公开(公告)号：US10707132B2

公开(公告)日：2020-07-07

申请号：US16557195

申请日：2019-08-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  Lam Research Corporation

Inventor： Georges Jacobi ,  Vimal K. Kamineni ,  Randolph F. Knarr ,  Balasubramanian Pranatharthiharan ,  Muthumanickam Sankarapandian

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/40

Abstract: After forming a material stack including a gate dielectric, a work function metal and a cobalt gate electrode in a gate cavity formed by removing a sacrificial gate structure, the cobalt gate electrode is recessed by oxidizing the cobalt gate electrode to provide a cobalt oxide layer on a surface of the cobalt gate electrodes and removing the cobalt oxide layer from the surface of the cobalt gate electrodes by a chemical wet etch. The oxidation and oxide removal steps can be repeated until the cobalt gate electrode is recessed to any desired thickness. The work function metal can be recessed after the recessing of the cobalt gate electrode is completed or during the recessing of the cobalt gate electrode.

公开(公告)号：US20190385912A1

公开(公告)日：2019-12-19

申请号：US16557128

申请日：2019-08-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  Lam Research Corporation

Inventor： Georges Jacobi ,  Vimal K. Kamineni ,  Randolph F. Knarr ,  Balasubramanian Pranatharthiharan ,  Muthumanickam Sankarapandian

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/40 ,  H01L21/28

Abstract: After forming a material stack including a gate dielectric, a work function metal and a cobalt gate electrode in a gate cavity formed by removing a sacrificial gate structure, the cobalt gate electrode is recessed by oxidizing the cobalt gate electrode to provide a cobalt oxide layer on a surface of the cobalt gate electrodes and removing the cobalt oxide layer from the surface of the cobalt gate electrodes by a chemical wet etch. The oxidation and oxide removal steps can be repeated until the cobalt gate electrode is recessed to any desired thickness. The work function metal can be recessed after the recessing of the cobalt gate electrode is completed or during the recessing of the cobalt gate electrode.

公开(公告)号：US10325848B2

公开(公告)日：2019-06-18

申请号：US16127645

申请日：2018-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V. V. S. Surisetty ,  Ruilong Xie

IPC: H01L29/49 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/088

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

公开(公告)号：US10236253B2

公开(公告)日：2019-03-19

申请号：US15484309

申请日：2017-04-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V. V. S. Surisetty ,  Ruilong Xie

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/417

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

公开(公告)号：US20180323110A1

公开(公告)日：2018-11-08

申请号：US16038426

申请日：2018-07-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Huiming Bu ,  Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L27/088 ,  H01L29/417 ,  H01L21/3213

CPC classification number: H01L21/823475 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

公开(公告)号：US10109722B2

公开(公告)日：2018-10-23

申请号：US15447210

申请日：2017-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Zhenxing Bi ,  Pietro Montanini ,  Eric R. Miller ,  Balasubramanian Pranatharthiharan ,  Oleg Gluschenkov ,  Ruqiang Bao ,  Kangguo Cheng

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/3105

Abstract: The disclosure relates to methods of forming etch-resistant spacers in an integrated circuit (IC) structure. Methods according to the disclosure can include: forming a mask on an upper surface of a gate structure positioned over a substrate; forming a spacer material on the substrate, the mask, and exposed sidewalls of the gate structure; forming a separation layer over the substrate and laterally abutting the spacer material to a predetermined height, such that an exposed portion of the spacer material is positioned above an upper surface of the separation layer and at least partially in contact with the mask; and implanting a dopant into the exposed portion of the spacer material to yield a dopant-implanted region within the spacer material, wherein the dopant-implanted region of the spacer material has a greater etch resistivity than a remainder of the spacer material.