公开(公告)号：US09076815B2

公开(公告)日：2015-07-07

申请号：US13907362

申请日：2013-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/266 ,  H01L21/8238

CPC classification number: H01L29/6653 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28008 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/7833

Abstract: A known problem when manufacturing transistors is the stress undesirably introduced by the spacers into the transistor channel region. In order to solve this problem, the present invention proposes an ion implantation aimed at relaxing the stress of the spacer materials. The relax implantation is performed after the spacer has been completely formed. The relax implantation may be performed after a silicidation process or after an implantation step in the source and drain regions followed by an activation annealing and before performing the silicidation process.

Abstract translation: 制造晶体管时的已知问题是由间隔物不期望地引入晶体管沟道区域的应力。 为了解决这个问题，本发明提出了一种旨在缓和间隔物材料的应力的离子注入。 在间隔件已经完全形成之后进行松弛植入。 松弛植入可以在硅化处理之后或在源极和漏极区域中的注入步骤之后进行激活退火并且在进行硅化处理之前进行。

公开(公告)号：US09040403B2

公开(公告)日：2015-05-26

申请号：US14244611

申请日：2014-04-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Stefan Flachowsky ,  Andy Wei

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/76895 ,  H01L21/76897

Abstract: Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode. The method includes removing the dummy gate electrode to form a trench bounded by the first and second sidewall spacers. The method removes an upper portion of the first sidewall spacer and deposits a layer of metal in the trench and over a remaining portion of the first sidewall spacer to form a gate electrode and an interconnect.

Abstract translation: 提供了用于制造包括门到活动触点的集成电路的方法。 一种方法包括形成虚拟栅极结构，其包括具有侧壁并覆盖半导体衬底的伪栅极电极以及虚设栅电极的侧壁上的第一和第二侧壁间隔物。 该方法包括去除伪栅电极以形成由第一和第二侧壁间隔物限定的沟槽。 该方法移除第一侧壁间隔物的上部，并将一层金属沉积在沟槽中并在第一侧壁间隔物的剩余部分上方形成栅电极和互连。

公开(公告)号：US09029214B2

公开(公告)日：2015-05-12

申请号：US13740974

申请日：2013-01-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sassiat ,  Ran Yan

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/823443 ,  H01L21/823468 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure. The method further includes depositing a non-conformal spacer material around the gate structure. A protection mask is formed over the non-conformal spacer material. The method etches the non-conformal spacer material and protection mask to form a salicidation spacer. Further, a self-aligned silicide contact is formed adjacent the salicidation spacer.

Abstract translation: 本文提供用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括在半导体衬底上形成栅极结构。 该方法还包括在栅极结构周围沉积非共形间隔物材料。 在非保形间隔物材料上形成保护罩。 该方法蚀刻非共形间隔物材料和保护掩模以形成防腐隔离物。 此外，邻近该盐化隔离层形成自对准的硅化物接触。

公开(公告)号：US20150102426A1

公开(公告)日：2015-04-16

申请号：US14052977

申请日：2013-10-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention relates to a semiconductor structure comprising at least a first and a second three-dimensional transistor, wherein the first transistor and the second transistor are electrically connected in parallel to each other, and wherein each transistor comprises a source and a drain, wherein the source and/or drain of the first transistor is at least partially separated from, respectively, the source and/or drain of the second transistor. The invention further relates to a process for realizing such a semiconductor structure.

Abstract translation: 本发明涉及包括至少第一和第二三维晶体管的半导体结构，其中第一晶体管和第二晶体管彼此并联电连接，并且其中每个晶体管包括源极和漏极，其中 第一晶体管的源极和/或漏极分别与第二晶体管的源极和/或漏极部分地分开。 本发明还涉及一种用于实现这种半导体结构的方法。

公开(公告)号：US09006045B2

公开(公告)日：2015-04-14

申请号：US13792950

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/41783 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78696

Abstract: A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode.

Abstract translation: 半导体结构包括衬底和晶体管。 晶体管包括设置在衬底上方的升高的源极区域和升高的漏极区域，一个或多个细长半导体管线，栅极电极和栅极绝缘层。 所述一个或多个细长半导体线连接在所述升高的源极区域和所述隆起的漏极区域之间，其中所述一个或多个细长半导体线路中的每一个的纵向方向基本上沿着垂直于所述衬底的厚度方向的水平方向延伸 。 每个细长半导体线包括沟道区。 栅电极围绕一个或多个细长半导体线路的每个沟道区域延伸。 栅极绝缘层设置在一个或多个细长半导体线路和栅电极中的每一个之间。

公开(公告)号：US20150021712A1

公开(公告)日：2015-01-22

申请号：US13946103

申请日：2013-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerd Zschaetzsch ,  Stefan Flachowsky ,  Dominic Thurmer

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/2254 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66803 ,  H01L29/7834 ,  H01L29/785

Abstract: The present disclosure provides in various aspects methods of forming a semiconductor device, methods for forming a semiconductor device structure, a semiconductor device and a semiconductor device structure. In some illustrative embodiments herein, a gate structure is formed over a non-planar surface portion of a semiconductor material provided on a surface of a substrate. A doped spacer-forming material is formed over the gate structure and the semiconductor material and dopants incorporated in the doped spacer-forming material are diffused into the semiconductor material close to a surface of the semiconductor material so as to form source/drain extension regions. The fabricated semiconductor devices may be multi-gate devices and, for example, comprise finFETs and/or wireFETs.

Abstract translation: 本公开在各方面提供了形成半导体器件的方法，形成半导体器件结构的方法，半导体器件和半导体器件结构。 在本文的一些说明性实施例中，栅极结构形成在设置在基板的表面上的半导体材料的非平面表面部分上。 掺杂的间隔物形成材料形成在栅极结构上，并且半导体材料和并入掺杂的间隔物形成材料中的掺杂剂被扩散到靠近半导体材料的表面的半导体材料中，以形成源极/漏极延伸区域。 制造的半导体器件可以是多栅极器件，并且例如包括finFET和/或wireFET。

公开(公告)号：US20150021693A1

公开(公告)日：2015-01-22

申请号：US13943521

申请日：2013-07-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stefan Flachowsky

IPC: H01L21/02 ,  H01L29/78

CPC classification number: H01L29/7843 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/3115 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823864

Abstract: When forming transistors with deuterium enhanced gate dielectrics and strained channel regions, the manufacturing processes of strain-inducing dielectric material layers formed above the transistors may be employed to efficiently introduce and diffuse the deuterium to the gate dielectrics. The incorporation of deuterium into the strain-inducing dielectric material layers may be accomplished on the basis of a deposition process in which deuterium is present in the process environment during deposition. The process temperature of the deposition process may be chosen to perform—in combination with further subsequently performed process steps—a sufficient diffusion of deuterium to the gate dielectrics.

Abstract translation: 当用氘增强的栅极电介质和应变通道区形成晶体管时，可以使用在晶体管上方形成的应变诱导电介质材料层的制造工艺来有效地将氘引入和扩散到栅极电介质。 应变诱导电介质材料层中的氘结合可以在沉积过程中基于沉积过程中完成沉积过程，其中氘存在于工艺环境中。 可以选择沉积工艺的工艺温度以与进一步随后执行的工艺步骤相结合 - 将氘充分扩散到栅极电介质。

公开(公告)号：US08835936B2

公开(公告)日：2014-09-16

申请号：US13678124

申请日：2012-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Ralf Illgen

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L21/2257 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/66628

Abstract: A method comprises providing a semiconductor structure comprising a substrate, an electrically insulating layer on the substrate and a semiconductor feature on the electrically insulating layer. A gate structure is formed on the semiconductor feature. An in situ doped semiconductor material is deposited on portions of the semiconductor feature adjacent the gate structure. Dopant is diffused from the in situ doped semiconductor material into the portions of the semiconductor feature adjacent the gate structure, the diffusion of the dopant into the portions of the semiconductor feature adjacent the gate structure forming doped source and drain regions in the semiconductor feature.

Abstract translation: 一种方法包括提供包括衬底，在衬底上的电绝缘层和电绝缘层上的半导体特征的半导体结构。 在半导体特征上形成栅极结构。 原位掺杂的半导体材料沉积在与栅极结构相邻的半导体器件的部分上。 掺杂剂从原位掺杂的半导体材料扩散到与栅极结构相邻的半导体器件的部分，掺杂剂扩散到半导体器件的与栅极结构相邻的部分，形成半导体器件中的掺杂源极和漏极区。

公开(公告)号：US20140246698A1

公开(公告)日：2014-09-04

申请号：US13783517

申请日：2013-03-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stefan Flachowsky ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823418 ,  H01L21/28518 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/66431 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: When forming sophisticated P-channel transistors, a semiconductor alloy layer is formed on the surface of the semiconductor layer including the transistor active region. When a metal silicide layer is formed contiguous to this semiconductor alloy layer, an agglomeration of the metal silicide layer into isolated clusters is observed. In order to solve this problem, the present invention proposes a method and a semiconductor device wherein the portion of the semiconductor alloy layer lying on the source and drain regions of the transistor is removed before formation of the metal silicide layer is performed. In this manner, the metal silicide layer is formed so as to be contiguous to the semiconductor layer, and not to the semiconductor alloy layer.

Abstract translation: 当形成复杂的P沟道晶体管时，在包括晶体管有源区的半导体层的表面上形成半导体合金层。 当与该半导体合金层邻接形成金属硅化物层时，观察到金属硅化物层与分离的团簇的聚集。 为了解决这个问题，本发明提出一种方法和半导体器件，其中在形成金属硅化物层之前去除位于晶体管的源极和漏极区域上的半导体合金层的部分。 以这种方式，金属硅化物层形成为与半导体层邻接，而不形成为半导体合金层。

公开(公告)号：US20140197498A1

公开(公告)日：2014-07-17

申请号：US13740974

申请日：2013-01-14

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sasiat ,  Ran Yan

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/823443 ,  H01L21/823468 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure. The method further includes depositing a non-conformal spacer material around the gate structure. A protection mask is formed over the non-conformal spacer material. The method etches the non-conformal spacer material and protection mask to form a salicidation spacer. Further, a self-aligned silicide contact is formed adjacent the salicidation spacer.

Abstract translation: 本文提供用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括在半导体衬底上形成栅极结构。 该方法还包括在栅极结构周围沉积非共形间隔物材料。 在非保形间隔物材料上形成保护罩。 该方法蚀刻非共形间隔物材料和保护掩模以形成防腐隔离物。 此外，邻近该盐化隔离层形成自对准的硅化物接触。