公开(公告)号：US08691470B2

公开(公告)日：2014-04-08

申请号：US12292078

申请日：2008-11-12

申请人： Ananda H. Kumar ,  Dien Nguyen ,  Martin Janousek ,  Tad Armstrong

发明人： Ananda H. Kumar ,  Dien Nguyen ,  Martin Janousek ,  Tad Armstrong

IPC分类号： C03C8/00 ,  H01M2/08 ,  H01M2/14

CPC分类号： H01M8/0286 ,  C03C8/02 ,  C03C8/24 ,  H01M8/0282 ,  H01M8/1246 ,  H01M2008/1293 ,  Y02E60/50

摘要： A seal composition includes a first alkaline earth metal oxide, a second alkaline earth metal oxide which is different from the first alkaline earth metal oxide, aluminum oxide, and silica in an amount such that molar percent of silica in the composition is at least five molar percent greater than two times a combined molar percent of the first alkaline earth metal oxide and the second alkaline earth metal oxide. The composition is substantially free of boron oxide and phosphorus oxide. The seal composition forms a glass ceramic seal which includes silica containing glass cores located in a crystalline matrix comprising barium aluminosilicate, and calcium aluminosilicate crystals located in the glass cores.

摘要翻译： 密封组合物包括第一碱土金属氧化物，与第一碱土金属氧化物不同的第二碱土金属氧化物，氧化铝和二氧化硅，其量使得组合物中二氧化硅的摩尔百分比为至少五摩尔 百分比大于第一碱土金属氧化物和第二碱土金属氧化物的组合摩尔百分数的两倍。 该组合物基本上不含氧化硼和氧化磷。 密封组合物形成玻璃陶瓷密封件，其包括位于包括硅铝酸钡的晶体基质中的含二氧化硅的玻璃核心和位于玻璃核心中的硅铝酸钙晶体。

公开(公告)号：US20120222960A1

公开(公告)日：2012-09-06

申请号：US13409950

申请日：2012-03-01

申请人： Ananda H. Kumar ,  Jorge Sotelo Albarran ,  Adam L. Cohen ,  Kieun Kim ,  Michael S. Lockard ,  Uri Frodis ,  Dennis R. Smalley

发明人： Ananda H. Kumar ,  Jorge Sotelo Albarran ,  Adam L. Cohen ,  Kieun Kim ,  Michael S. Lockard ,  Uri Frodis ,  Dennis R. Smalley

IPC分类号： C25D5/02

CPC分类号： B81C1/00666 ,  C25D5/022

摘要： Electrochemical fabrication processes and apparatus for producing single layer or multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers includes operations for reducing stress and/or curvature distortion when the structure is released from a sacrificial material which surrounded it during formation and possibly when released from a substrate on which it was formed. Six primary groups of embodiments are presented which are divide into eleven primary embodiments. Some embodiments attempt to remove stress to minimize distortion while others attempt to balance stress to minimize distortion.

摘要翻译： 用于生产单层或多层结构的电化学制造方法和装置，其中每个层包括至少两种材料的沉积，并且其中形成至少一些层包括当结构被释放时减少应力和/或曲率失真的操作 牺牲材料，其在形成期间包围它，并且可能当从其形成的基底释放时。 呈现了六个主要实施例的组，它们分为十一个主要实施例。 一些实施例尝试去除应力以最小化失真，而另一些实施例试图平衡应力以最小化失真。

公开(公告)号：US20120114861A1

公开(公告)日：2012-05-10

申请号：US13253856

申请日：2011-10-05

申请人： Adam L. Cohen ,  Uri Frodis ,  Michael S. Lockard ,  Ananda H. Kumar ,  Gang Zhang ,  Dennis R. Smalley

发明人： Adam L. Cohen ,  Uri Frodis ,  Michael S. Lockard ,  Ananda H. Kumar ,  Gang Zhang ,  Dennis R. Smalley

IPC分类号： B05D3/12 ,  B05D1/36 ,  C25D5/48

CPC分类号： C25D1/003 ,  B81C1/00492 ,  B81C99/0065 ,  B81C2201/0104 ,  B81C2201/0197 ,  C25D5/02 ,  C25D5/022 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76885

摘要： Electrochemical fabrication methods for forming single and multilayer mesoscale and microscale structures include the use of diamond machining (e.g. fly cutting or turning) to planarize layers. Some embodiments focus on systems of sacrificial and structural materials which can be diamond machined with minimal tool wear (e.g. Ni—P and Cu, Au and Cu, Cu and Sn, Au and Cu, Au and Sn, and Au and Sn—Pb). Some embodiments provide for reducing tool wear when using difficult-to-machine materials by (1) depositing difficult to machine materials selectively and potentially with little excess plating thickness and/or (2) pre-machining depositions to within a small increment of desired surface level (e.g. using lapping) and then using diamond fly cutting to complete the process, and/or (3) forming structures or portions of structures from thin walled regions of hard-to-machine material as opposed to wide solid regions of structural material.

摘要翻译： 用于形成单层和多层中尺度和微结构结构的电化学制造方法包括使用金刚石加工（例如飞切或车削）来平坦化层。 一些实施例侧重于牺牲和结构材料的系统，其可以以最小的工具磨损（例如Ni-P和Cu，Au和Cu，Cu和Sn，Au和Cu，Au和Sn以及Au和Sn-Pb）进行金刚石加工， 。 一些实施例提供了通过（1）选择性地沉积难以加工的材料并且潜在地以很少的镀层厚度沉积和/​​或（2）预加工沉积到期望表面的小增量内，以便在使用难加工材料时减少刀具磨损 （例如使用研磨），然后使用金刚石飞切切割来完成该过程，和/或（3）从硬质材料的薄壁区域形成与结构材料的宽固体区域相反的结构或部分结构。

公开(公告)号：US08030119B2

公开(公告)日：2011-10-04

申请号：US12399248

申请日：2009-03-06

申请人： Tirunelveli S. Ravi ,  Ananda H. Kumar ,  Ashish Asthana

发明人： Tirunelveli S. Ravi ,  Ananda H. Kumar ,  Ashish Asthana

IPC分类号： H01L21/00

CPC分类号： H01L31/1876 ,  H01L21/68728 ,  H01L31/048 ,  H01L31/068 ,  H01L31/1804 ,  H01L31/1892 ,  Y02E10/50 ,  Y02E10/547 ,  Y02P70/521

摘要： A method for fabricating a photovoltaic (PV) cell panel wherein all PV cells are formed simultaneously on a two-dimensional array of monocrystalline silicon mother wafers affixed to a susceptor is disclosed. Porous silicon separation layers are anodized in the surfaces of the mother wafers. The porous film is then smoothed to form a suitable surface for epitaxial film growth. An epitaxial reactor is used to grow n- and p-type films forming the PV cell structures. Contacts to the n- and p-layers are deposited, followed by gluing of a glass layer to the PV cell array. The porous silicon film is then separated by exfoliation in a peeling motion across all the cells attached together above, followed by attaching a strengthening layer on the PV cell array. The array of mother wafers may be reused multiple times, thereby reducing materials costs for the completed solar panels.

摘要翻译： 公开了一种制造光伏（PV）电池板的方法，其中所有PV电池同时形成在固定在基座上的单晶硅母晶片的二维阵列上。 在母晶片的表面上阳极氧化多孔硅分离层。 然后使多孔膜平滑以形成用于外延膜生长的合适表面。 使用外延反应器来生长形成PV电池结构的n型和p型膜。 与n层和p层的接触被沉积，然后将玻璃层粘合到PV电池阵列上。 然后通过剥离运动将多孔硅膜分离穿过所有附着在上面的细胞，然后在PV电池阵列上附加强化层。 母晶片的阵列可以重复使用多次，从而减少完成的太阳能电池板的材料成本。

公开(公告)号：US20110147223A1

公开(公告)日：2011-06-23

申请号：US13006814

申请日：2011-01-14

申请人： Ananda H. Kumar ,  Jorge Sotelo Alberran ,  Adam L. Cohen ,  Kieun Kim ,  Michael S. Lockard ,  Uri Frodis ,  Dennis R. Smalley

发明人： Ananda H. Kumar ,  Jorge Sotelo Alberran ,  Adam L. Cohen ,  Kieun Kim ,  Michael S. Lockard ,  Uri Frodis ,  Dennis R. Smalley

IPC分类号： C25D5/48 ,  C25D5/10

CPC分类号： B81C1/00666 ,  C25D5/022

摘要： Electrochemical fabrication processes and apparatus for producing single layer or multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers includes operations for reducing stress and/or curvature distortion when the structure is released from a sacrificial material which surrounded it during formation and possibly when released from a substrate on which it was formed. Six primary groups of embodiments are presented which are divide into eleven primary embodiments. Some embodiments attempt to remove stress to minimize distortion while others attempt to balance stress to minimize distortion.

摘要翻译： 用于生产单层或多层结构的电化学制造方法和装置，其中每个层包括至少两种材料的沉积，并且其中形成至少一些层包括当结构被释放时减少应力和/或曲率失真的操作 牺牲材料，其在形成期间包围它，并且可能当从其形成的基底释放时。 呈现了六个主要实施例的组，它们分为十一个主要实施例。 一些实施例尝试去除应力以最小化失真，而另一些实施例试图平衡应力以最小化失真。

公开(公告)号：US20100090339A1

公开(公告)日：2010-04-15

申请号：US12558486

申请日：2009-09-11

申请人： Ananda H. Kumar ,  Ashish Asthana ,  Farooq Quadri

发明人： Ananda H. Kumar ,  Ashish Asthana ,  Farooq Quadri

IPC分类号： H01L23/48 ,  H05K1/11

CPC分类号： H01L21/486 ,  G01R1/0491 ,  G01R3/00 ,  G01R31/2601 ,  H01L21/4807 ,  H01L21/4857 ,  H01L21/4867 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15312 ,  H05K1/111 ,  H05K3/4007 ,  H05K3/4629 ,  H05K2201/0367 ,  H05K2203/308 ,  H01L2924/00 ,  H01L2924/00014

摘要： This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of semiconductor devices. In some embodiments, such structures are shown to be useful for simultaneously testing multiple devices on a semiconductor wafer, or for assembling multiple substrates on to a wafer, to accomplish both testing and packaging of the dies on the wafer. In yet another embodiment of the invention, single or multilevel ceramic interconnect structures with thick film metal conductors, are fabricated right on the product wafer to facilitate economical testing and packaging of the dies on the wafer.

公开(公告)号：US20100068837A1

公开(公告)日：2010-03-18

申请号：US12558490

申请日：2009-09-11

申请人： Ananda H. Kumar ,  Ashish Asthana ,  Farooq Quadri

发明人： Ananda H. Kumar ,  Ashish Asthana ,  Farooq Quadri

IPC分类号： H01L21/66 ,  H01L21/768

CPC分类号： H01L21/486 ,  G01R1/0491 ,  G01R3/00 ,  G01R31/2601 ,  H01L21/4807 ,  H01L21/4857 ,  H01L21/4867 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15312 ,  H05K1/111 ,  H05K3/4007 ,  H05K3/4629 ,  H05K2201/0367 ,  H05K2203/308 ,  H01L2924/00 ,  H01L2924/00014

摘要： This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of semiconductor devices. In some embodiments, such structures are shown to be useful for simultaneously testing multiple devices on a semiconductor wafer, or for assembling multiple substrates on to a wafer, to accomplish both testing and packaging of the dies on the wafer. In yet another embodiment of the invention, single or multilevel ceramic interconnect structures with thick film metal conductors, are fabricated right on the product wafer to facilitate economical testing and packaging of the dies on the wafer.

摘要翻译： 本文件描述了具有一层或多层内部厚膜金属导体图案的多层陶瓷衬底的制造和使用，其中与衬底的一个或两个主表面相交的任何或全部金属通孔延伸出 用于制造柔性，暂时或永久互连的表面到电子部件的端子。 这种结构对于半导体器件的晶片探测和封装是有用的。 在一些实施例中，这样的结构被证明可用于同时测试半导体晶片上的多个器件，或用于将多个衬底组装到晶片上，以实现晶片上的管芯的测试和封装。 在本发明的另一个实施例中，具有厚膜金属导体的单层或多层陶瓷互连结构恰好在产品晶片上制造，以便于在晶片上经济地测试和封装管芯。

公开(公告)号：US20090320990A1

公开(公告)日：2009-12-31

申请号：US12431680

申请日：2009-04-28

申请人： Adam L. Cohen ,  Ananda H. Kumar ,  Michael S. Lockard ,  Dennis R. Smalley

发明人： Adam L. Cohen ,  Ananda H. Kumar ,  Michael S. Lockard ,  Dennis R. Smalley

IPC分类号： B32B37/00 ,  B32B38/10

CPC分类号： G01R3/00 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  C25D5/02 ,  C25D5/10 ,  G01R1/06716 ,  G01R1/06744 ,  G01R1/06755 ,  H01L21/4853

摘要： Some embodiments of the invention are directed to the electrochemical fabrication of microprobes which are formed from a core material and a material that partially coats the surface of the probe. Other embodiments are directed to the electrochemical fabrication of microprobes which are formed from a core material and a material that completely coats the surface of each layer from which the probe is formed including interlayer regions. These first two groups of embodiments incorporate both the core material and the coating material during the formation of each layer. Still other embodiments are directed to the electrochemical fabrication of microprobe arrays that are partially encapsulated by a dielectric material during a post layer formation coating process. In even further embodiments, the electrochemical fabrication of microprobes from two or more materials may occur by incorporating a coating material around each layer of the structure without locating the coating material in inter-layer regions.

摘要翻译： 本发明的一些实施方案涉及由芯材料和部分涂覆探针的表面的材料形成的微针的电化学制造。 其它实施方案涉及由核心材料形成的微结构的电化学制造，以及完全涂覆形成探针的每个层的表面的材料，包括中间层区域。 这些前两组实施例在形成每个层期间都包括芯材料和涂层材料。 其他实施例涉及在后层形成涂覆工艺期间由电介质材料部分封装的微探针阵列的电化学制造。 在甚至进一步的实施方案中，来自两种或更多种材料的微结构的电化学制造可以通过在结构的每一层周围并入涂层材料而不将涂层材料定位在层间区域中而进行。

公开(公告)号：US06370006B1

公开(公告)日：2002-04-09

申请号：US09506423

申请日：2000-02-17

申请人： Ananda H. Kumar ,  Kadthala Narendrnath ,  Shamouil Shamouilian

发明人： Ananda H. Kumar ,  Kadthala Narendrnath ,  Shamouil Shamouilian

IPC分类号： H02N1300

CPC分类号： H01L21/67109 ,  H01L21/6831 ,  H01L21/6833 ,  H02N13/00

摘要： An electrostatic chuck and a process of manufacturing an electrostatic chuck for supporting a semiconductor wafer during wafer processing and for providing a plurality of gas inlet channels extending through the chuck and through which thermal transfer gas can be supplied to the back side of the wafer to enhance the thermal transfer between the wafer and the chuck, embedding a plurality of inserts in a ceramic electrostatic chuck, each insert comprising a matrix of the ceramic of which the electrostatic chuck is made and a plurality of removable elongate members, and removing the elongate members to form a plurality of elongate holes providing the plurality of gas inlet channels.

摘要翻译： 一种静电卡盘和制造用于在晶片加工期间支撑半导体晶片的静电卡盘的工艺，以及用于提供延伸穿过卡盘的多个气体入口通道，并且热传递气体可以通过该导入通道提供到晶片的背面以增强 在晶片和卡盘之间的热传递，将多个插入件嵌入陶瓷静电卡盘中，每个插入件包括其上形成有静电卡盘的陶瓷基体和多个可移除的细长构件，并且将细长构件移除到 形成多个提供多个气体入口通道的细长孔。

公开(公告)号：US06267839B1

公开(公告)日：2001-07-31

申请号：US09229509

申请日：1999-01-12

申请人： Shamouil Shamouilian ,  Ananda H. Kumar ,  Arnold Kholodenko

发明人： Shamouil Shamouilian ,  Ananda H. Kumar ,  Arnold Kholodenko

IPC分类号： C23C1600

CPC分类号： B23Q3/154 ,  H01L21/6833 ,  Y10T279/23

摘要： A susceptor for a wafer support of a semiconductor processing chamber having multiple parallel electrical contacts between an RF electrode and a thick robust electrode near a bottom of the susceptor. The thick robust electrode has a low resistance and, therefore, evenly distributes RF power over its area. The multiple parallel contacts ensure that the RF power is also uniformly distributed across an area of the RF electrode. A plurality of electrically conductive vias extending between the robust electrode and the RF electrode make a plurality of parallel electrical contacts therebetween. Generally, the robust electrode is attached to a bottom side of the susceptor and is aligned substantially parallel to the RF electrode. An insulator plate is attached to a bottom of the susceptor for electrically isolating the robust electrode for the pedestal.

摘要翻译： 用于半导体处理室的晶片支架的感受体，其在RF电极和靠近基座的底部的厚坚固电极之间具有多个平行的电触点。 厚坚固的电极具有低电阻，因此在其区域上均匀分布RF功率。 多个并联触点确保RF功率也均匀分布在RF电极的一个区域上。 在坚固电极和RF电极之间延伸的多个导电通孔在它们之间形成多个平行的电接触。 通常，坚固的电极附接到基座的底侧，并且基本上平行于RF电极排列。 绝缘板连接到基座的底部，用于电绝缘基座的坚固电极。