公开(公告)号：US6058051A

公开(公告)日：2000-05-02

申请号：US901660

申请日：1997-07-28

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C7/00

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

摘要： The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuit. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

摘要翻译： 多个浮栅型MOSFET的电流路径串联连接形成串联电路。 该串联电路一端连接以接收参考电压，并连接到数据编程和读出电路。 在数据编程模式下，电子从浮置栅极放电到MOSFET的漏极，或者将漏极注入到浮动栅极中。 数据读出操作通过检查电流是否从串联电路的另一端流向一端来实现。

公开(公告)号：US5877982A

公开(公告)日：1999-03-02

申请号：US848227

申请日：1997-04-29

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

摘要： The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuit. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

摘要翻译： 多个浮栅型MOSFET的电流路径串联连接形成串联电路。 该串联电路一端连接以接收参考电压，并连接到数据编程和读出电路。 在数据编程模式下，电子从浮置栅极放电到MOSFET的漏极，或者将漏极注入到浮动栅极中。 数据读出操作通过检查电流是否从串联电路的另一端流向一端来实现。

公开(公告)号：US5517449A

公开(公告)日：1996-05-14

申请号：US433072

申请日：1995-05-03

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C11/34

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

摘要： The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuit. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

公开(公告)号：US5336952A

公开(公告)日：1994-08-09

申请号：US67102

申请日：1993-05-26

申请人： Hiroshi Iwahashi ,  Toshiyuki Fujimoto ,  Akira Narita

发明人： Hiroshi Iwahashi ,  Toshiyuki Fujimoto ,  Akira Narita

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C8/08 ,  G11C16/06 ,  G11C16/12 ,  H03K17/10 ,  H03K17/687

CPC分类号： G11C5/145 ,  G11C16/12 ,  G11C8/08 ,  H03K17/102

摘要： A semiconductor integrated circuit which is protected from element breakdown includes a memory cell, series-connected first and second program load transistors arranged between the memory cell and the program power source, a boosting circuit for outputting a board voltage higher than the voltage of a program power source, and a controller. The controller applies the boosted voltage to the gates of the first and second program load transistors when program data is set at a first logic level. The controller applies a voltage of about 0 V to the gate of the first program load transistor and an intermediate voltage lower than the voltage of the program power source and higher than 0 V to the gate of the second load transistor when the program data is set at a second logic level.

摘要翻译： 防止元件击穿的半导体集成电路包括布置在存储单元和编程电源之间的存储单元，串联连接的第一和第二程序负载晶体管，用于输出高于程序电压的电路板电压的升压电路 电源和控制器。 当程序数据被设置在第一逻辑电平时，控制器将升压电压施加到第一和第二编程负载晶体管的栅极。 当程序数据被设置时，控制器向第一编程负载晶体管的栅极施加大约0V的电压和低于编程电源电压的中间电压并且高于0V到第二负载晶体管的栅极 在第二逻辑级别。

公开(公告)号：US4613957A

公开(公告)日：1986-09-23

申请号：US514350

申请日：1983-07-15

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C7/00 ,  G11C7/06 ,  G01R19/00 ,  G11C7/02

CPC分类号： G11C7/067 ,  G11C7/00 ,  G11C7/065

摘要： A semiconductor memory device has a memory circuit with a plurality of memory cells, a data transmission line for transmitting the data from the memory circuit, and a data detection circuit for detecting the memory data supplied through the data transmission line. The data detection circuit produces output data in accordance with the direction of change in logic level of the memory data supplied through the data transmission line.

摘要翻译： 半导体存储器件具有多个存储器单元的存储器电路，用于从存储器电路发送数据的数据传输线以及用于检测通过数据传输线提供的存储器数据的数据检测电路。 数据检测电路根据通过数据传输线提供的存储器数据的逻辑电平的变化方向产生输出数据。

公开(公告)号：US4546455A

公开(公告)日：1985-10-08

申请号：US446669

申请日：1982-12-03

申请人： Hiroshi Iwahashi ,  Kiyofumi Ochii

发明人： Hiroshi Iwahashi ,  Kiyofumi Ochii

IPC分类号： G11C29/00 ,  G11C11/40

CPC分类号： G11C29/785 ,  G11C29/83

摘要： A programming circuit used with a semiconductor memory comprising normal as well as spare memory cells allows any of the normal memory cells to be replaced by a spare memory cell and includes a fuse and a MOSFET connected in series between first and second power supply terminals. A voltage signal at the junction between the fuse and the MOSFET is delivered to the gate of the MOSFET after being delayed after power is supplied.

摘要翻译： 与包括正常以及备用存储单元的半导体存储器一起使用的编程电路允许任何正常存储器单元被备用存储单元替换，并且包括串联连接在第一和第二电源端子之间的保险丝和MOSFET。 保险丝和MOSFET之间的连接处的电压信号在供电后被延迟后传送到MOSFET的栅极。

公开(公告)号：US06528012B2

公开(公告)日：2003-03-04

申请号：US09820862

申请日：2001-03-30

申请人： Kazutoshi Nishimoto ,  Naoshige Kubo ,  Hiroshi Iwahashi ,  Shuji Yamamoto ,  Hidefumi Yamanaka ,  Shinji Koga ,  Yutaka Chida ,  Taketo Yamakawa ,  Kouji Michiba ,  Hiroyuki Hirata ,  Kazuhiro Ogawa ,  Toshinobu Nishibata

发明人： Kazutoshi Nishimoto ,  Naoshige Kubo ,  Hiroshi Iwahashi ,  Shuji Yamamoto ,  Hidefumi Yamanaka ,  Shinji Koga ,  Yutaka Chida ,  Taketo Yamakawa ,  Kouji Michiba ,  Hiroyuki Hirata ,  Kazuhiro Ogawa ,  Toshinobu Nishibata

IPC分类号： C22C3808

CPC分类号： C22C38/105 ,  B23K35/3033 ,  B23K35/3066 ,  C22C38/005 ,  C22C38/08 ,  C22C38/12 ,  C22C38/14 ,  Y10T428/12951 ,  Y10T428/12958 ,  Y10T428/12965

摘要： In a welded structure and welded pipe, having members joined to each other by welding wherein, at least one of the members is formed of Fe—Ni-base low thermal expansion coefficient alloy, there is provided a welded structure and welded pipe having a weld metal free from cracking and achieving an excellent toughness and stress corrosion cracking resistance. Further, a welding material is provided which can form such a weld metal and is excellent in workability and weldability in fabrication. The weld metal comprises, on the weight % basis, Ni: 30 to 45%, Co: 0 to 10%, C: 0.03 to 0.5%, Mn: 0.7% or less, either one of or the total of Nb and Zr: 0.05 to 4%, and rare earth element: 0 to 0.5%, with impurities being P: 0.02% or less, Al: 0.01% or less, and oxygen: 0.01% or less, wherein each of Si and S satisfies the following formulas {circle around (1)} and {circle around (2)}, where each element symbol in the following formulas {circle around (1)} and {circle around (2)} indicates the content (weight %) of each element. Si≦0.1(Nb+Zr)+0.05%  {circle around (1)} S≦0.0015(Nb+Zr)+0.0055%  {circle around (2)}

摘要翻译： 在焊接结构和焊接管中，具有通过焊接彼此接合的构件，其中至少一个构件由Fe-Ni基低热膨胀系数合金形成，提供焊接结构和焊接管，其具有焊接 金属无裂纹，具有优异的韧性和应力腐蚀开裂性。 此外，提供了可以形成这种焊接金属的焊接材料，并且加工性和制造中的可焊接性优异。 焊接金属以重量％计含有：Ni：30〜45％，Co：0〜10％，C：0.03〜0.5％，Mn：0.7％以下，Nb和Zr： 0.05〜4％，稀土元素：0〜0.5％，杂质为P：0.02％以下，Al：0.01％以下，氧：0.01％以下，Si和S分别满足下式 {round around（1和{circle around（2，where each element symbol in the following formula {circle around（1 and {circle around（2表示每个元素的含量（重量％））。

公开(公告)号：US06353557B2

公开(公告)日：2002-03-05

申请号：US09823525

申请日：2001-03-30

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C1604

CPC分类号： G11C16/24 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/26

摘要： In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

公开(公告)号：US06304489B1

公开(公告)日：2001-10-16

申请号：US09537933

申请日：2000-03-29

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C700

CPC分类号： G11C16/24 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/26

摘要： In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

摘要翻译： 在非易失性半导体存储器中，在读取期间可以通过存储单元流过大电流。 可以减少列线的数量。 对各个存储单元的浮置栅极的电子注入被平均以减小其阈值电压的偏差。 来自相应存储单元的浮置栅极的电子发射也被平均以减小其阈值电压的偏差。 可以防止由于锁存电路引起的芯片尺寸的增加。 通过注意到二进制数据的多个“0”或“1”中的任何一个存储在存储器单元组或块的存储单元中，将负阈值电压分配给用于存储更多位侧的存储单元 二进制数据的数据。 对于两个相邻的存储器块，共同使用单列线。 为了将电子注入存储单元的浮动栅极，电压逐渐增加并且当电子注入到预定的注入速率时停止。 电子一次从浮动栅极发射，此后再次注入电子以存储二进制数据之一。 此外，数据锁存电路可以形成在远离存储单元阵列的任何位置处。

公开(公告)号：US06178116B1

公开(公告)日：2001-01-23

申请号：US09550791

申请日：2000-04-17

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

摘要： The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuit. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

摘要翻译： 多个浮栅型MOSFET的电流路径串联连接形成串联电路。 该串联电路一端连接以接收参考电压，并连接到数据编程和读出电路。 在数据编程模式下，电子从浮置栅极放电到MOSFET的漏极，或者将漏极注入到浮动栅极中。 数据读出操作通过检查电流是否从串联电路的另一端流向一端来实现。