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公开(公告)号：US07835171B2
公开(公告)日：2010-11-16
申请号：US12172198
申请日：2008-07-11
申请人： Kazuo Ono , Riichiro Takemura , Tomonori Sekiguchi
发明人： Kazuo Ono , Riichiro Takemura , Tomonori Sekiguchi
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C13/0011 , G11C13/0069 , G11C16/3468 , G11C2013/0066 , G11C2013/009 , G11C2213/52 , G11C2213/79
摘要： A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is connected in series with the resistance variable memory cell, and a sensor amplifier detects whether the potential at an intermediate node between the memory cell and the reference resistor exceeds a given threshold voltage, so as to stop the write operation based on a detection result.
摘要翻译： 电阻变化存储器减少了编程之后的电阻值的不均匀性，使得可以以高速度对存储器单元执行重写操作。 参考电阻与电阻变化存储单元串联连接，传感器放大器检测存储单元和参考电阻之间的中间节点处的电位是否超过给定阈值电压，以便基于 检测结果。
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公开(公告)号：US20090273961A1
公开(公告)日：2009-11-05
申请号：US12430067
申请日：2009-04-25
申请人： Kazuo ONO , Riichiro Takemura , Tomonori Sekiguchi
发明人： Kazuo ONO , Riichiro Takemura , Tomonori Sekiguchi
CPC分类号： G11C13/0023 , G11C7/18 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/00 , G11C13/0004 , G11C13/0026 , G11C13/0069 , G11C13/02 , G11C2013/0078 , G11C2213/79
摘要： A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and “0”. In the resistance change memory, bit lines are formed into a layered structure, the bit line select switches for connecting to the global bit line are provided at both ends of the local bit line, and a control method of the bit line select switches is changed in the writing and the reading, thereby realizing the optimum array configurations for each of them. More specifically, in the writing and the reading, two current paths are provided in parallel by turning ON the bit line select switches simultaneously.
摘要翻译： 在电阻改变存储器中提供一种用于在不增加电源电压的情况下增加重写电流并且还减少在重写之后的电阻状态的存储器阵列内的位置依赖性的技术，其中存储器单元的电阻值在逻辑值“1 “和”0“。 在电阻变化存储器中，将位线形成为分层结构，在本地位线的两端设置用于连接到全局位线的位线选择开关，并且位线选择开关的控制方式发生变化 在写入和读取中，从而实现它们中的每一个的最佳阵列配置。 更具体地，在写入和读取中，通过同时接通位线选择开关并联提供两个电流路径。
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公开(公告)号：US20090262574A1
公开(公告)日：2009-10-22
申请号：US12427392
申请日：2009-04-21
CPC分类号： G01R31/31715 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , G11C2213/71 , G11C2213/72 , Y10T29/49169
摘要： A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.
摘要翻译： 实现了高可靠性的大容量相变存储器模块。 根据本发明的半导体器件包括具有堆叠使用硫属化物材料的存储层和由二极管构成的存储单元的结构的存储器阵列，并且根据层来改变初始化条件和重写条件 其中所选择的存储器单元被定位。 根据操作选择电流镜电路，并且同时根据电压选择中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件） 电路和电流镜电路。
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公开(公告)号：US20090262568A1
公开(公告)日：2009-10-22
申请号：US12172198
申请日：2008-07-11
申请人： KAZUO ONO , Riichiro Takemura , Tomonori Sekiguchi
发明人： KAZUO ONO , Riichiro Takemura , Tomonori Sekiguchi
CPC分类号： G11C13/0064 , G11C13/0011 , G11C13/0069 , G11C16/3468 , G11C2013/0066 , G11C2013/009 , G11C2213/52 , G11C2213/79
摘要： A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is connected in series with the resistance variable memory cell, and a sensor amplifier detects whether the potential at an intermediate node between the memory cell and the reference resistor exceeds a given threshold voltage, so as to stop the write operation based on a detection result.
摘要翻译： 电阻变化存储器减少了编程之后的电阻值的不均匀性，使得可以以高速度对存储器单元执行重写操作。 参考电阻与电阻变化存储单元串联连接，传感器放大器检测存储单元和参考电阻之间的中间节点处的电位是否超过给定阈值电压，以便基于 检测结果。
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85.发明授权公开(公告)号：US07603592B2
公开(公告)日：2009-10-13
申请号：US11495550
申请日：2006-07-31
IPC分类号： G11C29/00
CPC分类号： G06F11/1044 , G11C2029/0409
摘要： A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.
摘要翻译： 提供了即使在小型化的情况下也能够实现足够的操作余量而不增加面积损失的半导体存储器件。 将由64位的数据位和9位的校验位构成的纠错系统引入到诸如DRAM的存储器阵列中，并且其中需要的纠错码电路设置在读出放大器阵列附近。 除了由这种存储器阵列组成的常规存储器阵列之外，在芯片中提供了具有读出放大器阵列和与其相邻的纠错码电路的冗余存储器阵列。 通过这种方式，可以更换制造过程中发生的错误。 此外，纠错码电路校正了激活命令时的错误，并且在预充电命令时存储检查位。
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公开(公告)号：US20090251948A1
公开(公告)日：2009-10-08
申请号：US12416432
申请日：2009-04-01
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
CPC分类号： G11C5/147 , G11C7/04 , G11C11/4076 , G11C11/4091 , G11C11/4097
摘要： In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes.
摘要翻译： 在半导体存储器件中，存储单元通过局部位线和全局位线与本地读出放大器和全局读出放大器连接。 本地读出放大器是包括单个MOS晶体管的单端读出放大器，其检测当与存储单元读取和写入数据时变化的局部位线的电位。 监视MOS晶体管的阈值电压，以产生高电平写入电压和低电平写入电压，这些电压根据监视结果进行校正和移位，从而通过对存储器单元适当地执行重新加载操作 全局局部感测放大器。 因此，可以消除阈值电压的温度变化和由于制造工艺的分散造成的阈值电压的偏移。
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公开(公告)号：US07582921B2
公开(公告)日：2009-09-01
申请号：US11504738
申请日：2006-08-16
IPC分类号： H01L27/10
CPC分类号： H01L27/10882 , G03F1/36 , H01L21/32139 , H01L23/528 , H01L27/105 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely. It is thus possible to prevent the resist pattern from separation and contact of adjacent patterns. Consequently, it is also possible to prevent break failures of patterned lines and short failures between those patterned lines.
摘要翻译： 在用于构图字和数据线的掩模图案（a）中，在相邻字线之间改变长度以便在其尖端处彼此偏移，此外，每个字线的尖端被倾斜地切割。 因此可以防止抗蚀剂图案与相邻图案分离和接触。 因此，也可以防止图案线的断裂故障和这些图案线之间的短路故障。
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公开(公告)号：US07574648B2
公开(公告)日：2009-08-11
申请号：US11194486
申请日：2005-08-02
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C11/401 , G11C29/42 , G11C29/44
摘要： When the miniaturization of a DRAM advances, the capacity of a cell capacitor decreases, and further the voltage of a data line is lowered, the amount of read signals remarkably lowers, errors are produced during readout, and the yield of chips lowers. To solve the above problems, the present invention provides a DRAM that: has an error correcting code circuit for each sub-array; detects and corrects errors with said error correcting code circuit in both the reading and writing operations; and further has rescue circuits in addition to said error correcting code circuits and replaces a defective cell caused by hard error with a redundant bit.
摘要翻译： 当DRAM的小型化进展时，单元电容器的容量减小，数据线的电压降低，读取信号量显着降低，读出时产生误差，芯片的产量降低。 为了解决上述问题，本发明提供一种具有每个子阵列的纠错码电路的DRAM， 在读取和写入操作中检测和纠正所述纠错码电路的错误; 并且除了所述纠错码电路之外还具有救援电路，并用冗余位代替由硬错误引起的故障单元。
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89.发明授权Memory device having high speed sense amplifier comprising pull-up circuit and pull-down circuits with drivability for each 失效具有高速读出放大器的存储器件包括具有每个驱动能力的上拉电路和下拉电路公开(公告)号：US07492655B2
公开(公告)日：2009-02-17
申请号：US11737693
申请日：2007-04-19
IPC分类号： G11C7/02
CPC分类号： G11C11/4091 , G11C7/065 , G11C2207/065 , H01L27/10897
摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。
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90.发明授权公开(公告)号：US07466577B2
公开(公告)日：2008-12-16
申请号：US11392805
申请日：2006-03-30
申请人： Tomonori Sekiguchi , Hideki Osaka , Tatemi Ido , Osamu Nagashima , Mitsuaki Katagiri , Ichiro Anjo
发明人： Tomonori Sekiguchi , Hideki Osaka , Tatemi Ido , Osamu Nagashima , Mitsuaki Katagiri , Ichiro Anjo
CPC分类号： G11C8/12 , G11C5/02 , G11C5/04 , G11C11/4074 , G11C11/4096 , H01L24/50
摘要： A semiconductor storage employs a base substrate (101) having a command/address external terminal group (CA), a data input/output external terminal group (DQ), and a single chip select external terminal (CS), and also comprises a plurality of memory chips (110) to (113) mounted on a base substrate (101), each of which can individually carry out read and write operations. The terminals (CA), (DQ), and (CS) are connected to an interface chip (120). The interface chip (120) has a chip select signal generation circuit that can individually activate a plurality of memory chips (110) to (113) on the basis of an address signal fed by way of the terminal (CA) and on the basis of a chip select signal fed by way of the terminal (CS).
摘要翻译： 半导体存储器使用具有命令/地址外部端子组（CA），数据输入/输出外部端子组（DQ）和单个芯片选择外部端子（CS）的基底（101），并且还包括多个 的安装在基板（101）上的存储芯片（110）至（113），每个可独立地进行读写操作。 端子（CA），（DQ）和（CS）连接到接口芯片（120）。 接口芯片（120）具有芯片选择信号生成电路，该电路可以基于通过终端（CA）馈送的地址信号，并基于以下方式单独激活多个存储器芯片（110）〜（113） 通过端子（CS）馈送的芯片选择信号。
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