公开(公告)号：US20080224118A1

公开(公告)日：2008-09-18

申请号：US12127994

申请日：2008-05-28

申请人： James P. Doyle ,  Bruce G. Elmegreen ,  Lia Krusin-Elbaum ,  Chung Hon Lam ,  Xiao Hu Liu ,  Dennis M. Newns ,  Christy S. Tyberg

发明人： James P. Doyle ,  Bruce G. Elmegreen ,  Lia Krusin-Elbaum ,  Chung Hon Lam ,  Xiao Hu Liu ,  Dennis M. Newns ,  Christy S. Tyberg

IPC分类号： H01L47/00

CPC分类号： H01L45/1233 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.

公开(公告)号：US07351648B2

公开(公告)日：2008-04-01

申请号：US11335372

申请日：2006-01-19

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Chung Hon Lam

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Chung Hon Lam

IPC分类号： H01L21/44 ,  H01L21/76

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76885

摘要： Methods for fabricating a semiconductor device include forming a first layer on an underlying layer, forming a hardmask on the first layer, and patterning holes through the hardmask and first layer. An overhang is formed extending over sides of the holes. A conformal layer is deposited over the overhang and in the holes until the conformal layer closes off the holes to form a void/seam in each hole. The void/seam in each hole is exposed by etching back a top surface. The void/seam in each hole is extended to the underlying layer.

摘要翻译： 制造半导体器件的方法包括在下层上形成第一层，在第一层上形成硬掩模，以及通过硬掩模和第一层图形化孔。 形成在孔的侧面上延伸的突出端。 保形层沉积在悬垂孔和孔中，直到共形层封闭孔，以在每个孔中形成空隙/接缝。 每个孔中的空隙/接缝通过蚀刻顶部表面而暴露出来。 每个孔中的空隙/接缝延伸到下层。

公开(公告)号：US07233177B2

公开(公告)日：2007-06-19

申请号：US11098078

申请日：2005-04-04

申请人： Louis C. Hsu ,  Brian L. Ji ,  Chung Hon Lam

发明人： Louis C. Hsu ,  Brian L. Ji ,  Chung Hon Lam

IPC分类号： H03K5/22 ,  G06G7/28

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0064 ,  G11C2013/0054

摘要： The present invention comprises a method and structure for programming an on-chip phase-change resistor to a target resistance. Using an off-chip precision resistor as a reference, a state-machine determines a difference between the resistance of an on-chip resistor and the target resistance. Based upon this difference, the state machine directs a pulse generator to apply set or reset pulses to the on-chip resistor in order to decrease or increase, respectively, the resistance of the resistor, as necessary. In order to program the resistance of the phase-change resistor to a tight tolerance, it is successively reset and set by applying progressively decreasing numbers of reset pulses and set pulses, respectively, until the number of set pulses is equal to one and the target resistance of the on-chip resistor is reached.

摘要翻译： 本发明包括用于将片上相变电阻器编程为目标电阻的方法和结构。 使用片外精密电阻器作为参考，状态机确定片上电阻器的电阻与目标电阻之间的差。 基于这种差异，状态机引导脉冲发生器将片上电阻器设置或复位脉冲施加到片上电阻器，以便根据需要分别降低或增加电阻器的电阻。 为了将相变电阻器的电阻编程为严格的公差，通过分别逐渐递减的复位脉冲数和设定脉冲数来连续复位和设置，直到设定脉冲数等于1，目标值 达到片上电阻的电阻。

公开(公告)号：US06548418B2

公开(公告)日：2003-04-15

申请号：US10158249

申请日：2002-05-30

申请人： Chung Hon Lam ,  Eric Seung Lee ,  Francis Roger White

发明人： Chung Hon Lam ,  Eric Seung Lee ,  Francis Roger White

IPC分类号： H01L21302

CPC分类号： H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/3185 ,  Y10S438/97

摘要： A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8. The second section, formed on top of the first section is formed with the ratio of the silicon to nitrogen of greater than about 0.8. Preferably the two sections together are from about 50 to about 100 nanometers thick.

公开(公告)号：US06504207B1

公开(公告)日：2003-01-07

申请号：US09609292

申请日：2000-06-30

申请人： Bomy A. Chen ,  Jay G. Harrington ,  Kevin M. Houlihan ,  Dennis Hoyniak ,  Chung Hon Lam ,  Hyun Koo Lee ,  Rebecca D. Mih ,  Jed H. Rankin

发明人： Bomy A. Chen ,  Jay G. Harrington ,  Kevin M. Houlihan ,  Dennis Hoyniak ,  Chung Hon Lam ,  Hyun Koo Lee ,  Rebecca D. Mih ,  Jed H. Rankin

IPC分类号： H01L2976

CPC分类号： H01L21/28273 ,  G11C16/0408 ,  H01L29/42328

摘要： A method and structure for a EEPROM memory device integrated with high performance logic or NVRAM. The EEPROM device includes a floating gate and program gate self-aligned with one another. During programming, electron tunneling occurs between the floating gate and the program gate.

摘要翻译： 与高性能逻辑或NVRAM集成的EEPROM存储器件的方法和结构。 EEPROM器件包括浮置栅极和彼此自对准的程序栅极。 在编程期间，在浮栅和程序门之间发生电子隧穿。

公开(公告)号：US08891293B2

公开(公告)日：2014-11-18

申请号：US13472395

申请日：2012-05-15

申请人： Pei-Ying Du ,  Chao-I Wu ,  Ming-Hsiu Lee ,  Sangbum Kim ,  Chung Hon Lam

发明人： Pei-Ying Du ,  Chao-I Wu ,  Ming-Hsiu Lee ,  Sangbum Kim ,  Chung Hon Lam

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0004 ,  G11C13/0021

摘要： Phase change based memory devices and methods for operating such devices described herein overcome the set or reset failure mode and result in improved endurance, reliability and data storage performance. A high current repair operation is carried out in response to a set or reset failure of a phase change memory cell. The higher current repair operation can provide a sufficient amount of energy to reverse compositional changes in the phase change material which can occur after repeated set and reset operations. By reversing these compositional changes, the techniques described herein can recover a memory cell which experienced a set or reset failure, thereby extending the endurance of the memory cell. In doing so, phase change based memory devices and methods for operating such devices are provided which have high cycle endurance.

摘要翻译： 基于相变的存储器件和用于操作这里描述的这种器件的方法克服了设置或复位故障模式并导致改进的耐久性，可靠性和数据存储性能。 响应于相变存储单元的置位或复位故障执行高电流修复操作。 更高的电流修复操作可以提供足够的能量来反转在重复设置和复位操作之后可能发生的相变材料的组成变化。 通过颠倒这些组合变化，本文描述的技术可以恢复经历设置或复位故障的存储器单元，从而延长存储单元的耐久性。 这样做，提供了具有高循环耐久性的基于相变的存储器件和用于操作这些器件的方法。

公开(公告)号：US08446748B2

公开(公告)日：2013-05-21

申请号：US13198292

申请日：2011-08-04

申请人： Chung Hon Lam ,  Jing Li ,  Robert Montoye

发明人： Chung Hon Lam ,  Jing Li ,  Robert Montoye

IPC分类号： G11C15/04

CPC分类号： G06F17/5077 ,  G11C5/06 ,  G11C11/412 ,  G11C15/04

摘要： What is disclosed is a novel memory array and process for creating a memory array to reduce wireline variability. The method includes accessing a routing design of a memory array with a plurality of memory cells. Each memory cell in the array includes one or more access devices, and a group of wires electrically connected between one or more of the memory cells and peripheral circuitry (PC). The group of the group of wires is divided into at least one subgroup (N). Next, a capacitance (C1, C2 . . . CN) of each wire in the subgroup (N) is calculated. Continuing further, a maximum capacitance (CMAX) of wires in the subgroup (N) is determined. An add-on capacitance to be added to a number (NA) of the wires in the subgroup (N) is calculated.

摘要翻译： 公开的是一种新颖的存储器阵列和用于创建存储器阵列以减少有线变化的过程。 该方法包括使用多个存储器单元访问存储器阵列的路由设计。 阵列中的每个存储单元包括一个或多个访问设备，以及电连接在一个或多个存储器单元和外围电路（PC）之间的一组电线。 该组电线分为至少一个子组（N）。 接下来，计算子组（N）中每根导线的电容（C1，C2 ... CN）。 进一步地，确定子组（N）中的导线的最大电容（CMAX）。 计算要添加到子组（N）中的数量（NA）的附加电容。

公开(公告)号：US08377789B2

公开(公告)日：2013-02-19

申请号：US12538146

申请日：2009-08-09

申请人： Gerhard Ingmar Meijer ,  Chung Hon Lam ,  Hon-Sum Phillip Wong

发明人： Gerhard Ingmar Meijer ,  Chung Hon Lam ,  Hon-Sum Phillip Wong

IPC分类号： H01L21/20

CPC分类号： H01L45/04 ,  H01L27/20 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/147 ,  H01L45/16

摘要： A method for fabricating a field-enhanced programmable resistance memory cell. In an example embodiment, a resistor includes a resistance structure between a first electrode and a second electrode. The resistance structure includes an insulating dielectric material. The second electrode includes a protrusion extending into the resistance structure. The insulating dielectric material includes a material in which a confined conductive region with a programmable resistance is formable via a conditioning signal.

摘要翻译： 一种用于制造场增强型可编程电阻存储单元的方法。 在示例性实施例中，电阻器包括在第一电极和第二电极之间的电阻结构。 电阻结构包括绝缘介电材料。 第二电极包括延伸到电阻结构中的突起。 绝缘电介质材料包括其中通过调节信号可形成具有可编程电阻的受限导电区域的材料。

公开(公告)号：US08017432B2

公开(公告)日：2011-09-13

申请号：US12684185

申请日：2010-01-08

申请人： Chung Hon Lam ,  Alejandro G. Schrott

发明人： Chung Hon Lam ,  Alejandro G. Schrott

IPC分类号： H01L21/06

CPC分类号： H01L45/1233 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1641 ,  H01L45/1683

摘要： A method for formation of a phase change memory (PCM) cell includes depositing amorphous phase change material in a via hole, the via hole comprising a bottom and a top, such that the amorphous phase change material is grown on an electrode located at the bottom of the via hole; melt-annealing the amorphous phase change material; and crystallizing the phase change material starting at the electrode at the bottom of the via hole and ending at the top of the via hole.

摘要翻译： 形成相变存储器（PCM）单元的方法包括在通孔中沉积非晶相变材料，该通孔包括底部和顶部，使得非晶相变材料在位于底部的电极上生长 的通孔; 对非晶相变材料进行熔融退火; 并且从通孔底部的电极开始并且以通孔的顶部结束，使相变材料结晶。

公开(公告)号：US07960808B2

公开(公告)日：2011-06-14

申请号：US11844109

申请日：2007-08-23

申请人： Geoffrey W. Burr ,  Chandrasekharan Kothandaraman ,  Chung Hon Lam ,  Xiao Hu Liu ,  Stephen M. Rossnagel ,  Christy S. Tyberg ,  Robert L. Wisnieff

发明人： Geoffrey W. Burr ,  Chandrasekharan Kothandaraman ,  Chung Hon Lam ,  Xiao Hu Liu ,  Stephen M. Rossnagel ,  Christy S. Tyberg ,  Robert L. Wisnieff

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.

摘要翻译： 集成电路中的可逆熔丝结构通过实现具有短路相变材料的熔断电池获得，所述相变材料与能够使电流通过相变材料线（熔丝电池）的通孔和线结构相接触。 电流通过熔丝电池，以便通过将结晶状态的相变材料加热至熔点，从而将材料从较小电阻的材料转变为更电阻的材料，然后快速将材料淬火成非晶状态。 可逆编程通过使较低电流通过熔丝电池来实现，以将高电阻率无定形材料转换成较低电阻率的晶体材料。 集成适当的感测电路以读取存储在熔丝中的信息，其中所述感测电路用于启用或禁用电路。