公开(公告)号：US20230187362A1

公开(公告)日：2023-06-15

申请号：US17548078

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Christopher M. Pelto ,  Kimin Jun ,  Brandon M. Rawlings ,  Shawna M. Liff ,  Bradley A. Jackson ,  Robert J. Munoz ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/5383 ,  H01L25/0652 ,  H01L23/49894 ,  H01L25/50 ,  H01L24/96

Abstract: A microelectronic assembly is provided, comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer; and a third plurality of IC dies in a third layer, in which: the second layer is between the first layer and the third layer, an interface between two adjacent layers comprises interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects, and each of the first layer, the second layer, and the third layer comprises a dielectric material, and further comprises conductive traces in the dielectric material.

公开(公告)号：US11676966B2

公开(公告)日：2023-06-13

申请号：US16354960

申请日：2019-03-15

Applicant: INTEL CORPORATION

Inventor： Gilbert W. Dewey ,  Jack T. Kavalieros ,  Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Kimin Jun ,  Patrick Morrow ,  Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/17 ,  H01L25/065 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/7851 ,  H01L2224/0401

Abstract: Disclosed herein are stacked transistors having device strata with different channel widths, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein different channel materials of different strata have different widths.

公开(公告)号：US20230170327A1

公开(公告)日：2023-06-01

申请号：US17538603

申请日：2021-11-30

Applicant: Intel Corporation

Inventor： Jin Yang ,  David Shia ,  Adel A. Elsherbini ,  Christopher M. Pelto ,  Kimin Jun ,  Bradley A. Jackson ,  Robert J. Munoz ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L25/0652 ,  H01L2225/06517 ,  H01L24/08

Abstract: A microelectronic assembly is provided, comprising: a first IC die coupled to a surface with first interconnects having a first pitch; and a second IC die coupled to the surface with second interconnects having a second pitch. The second pitch is greater than the first pitch, and the first pitch is less than 10 micrometers. In another embodiment, a microelectronic assembly is provided, comprising: a first stack coupled to a surface, the first stack comprising a first number of IC dies; and a second stack coupled to the surface, the second stack comprising a second number of IC dies, in which: the first stack and the second stack are laterally surrounded by a dielectric, the first stack and the second stack have a same thickness, and the first number is less than the second number.

公开(公告)号：US11658221B2

公开(公告)日：2023-05-23

申请号：US17522764

申请日：2021-11-09

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Rishabh Mehandru ,  Aaron D. Lilak ,  Kimin Jun

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L21/225 ,  H01L21/265

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L27/1266 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/78 ,  H01L29/785 ,  H01L21/2254 ,  H01L21/26513 ,  H01L29/66545

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20230091766A1

公开(公告)日：2023-03-23

申请号：US17483651

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Ved V. Gund ,  Kevin P. O'Brien ,  Kimin Jun ,  Edris Mohammed ,  Arnab Sen Gupta ,  Matthew V. Metz ,  Ibrahim L. Ban ,  Paul Fischer

IPC: H03H9/54 ,  H03H9/17 ,  H03H9/13 ,  H04B1/16

Abstract: In one embodiment, a resonator device includes a substrate comprising a piezoelectric material and a set of electrodes on the substrate. The electrodes are in parallel and a width of the electrodes is equal to a distance between the electrodes. The resonator device further includes a set of switches, with each switch coupled to a respective electrode. The switches are to connect to opposite terminals of an alternating current (AC) signal source and select between the terminals of the AC signal source based on an input signal.

公开(公告)号：US11605565B2

公开(公告)日：2023-03-14

申请号：US16236156

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Gilbert Dewey ,  Aaron Lilak ,  Kimin Jun ,  Brennen Mueller ,  Ehren Mannebach ,  Anh Phan ,  Patrick Morrow ,  Hui Jae Yoo ,  Jack T. Kavalieros

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423

Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor stacked above and self-aligned with a second transistor, where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode, a first channel layer including a first channel material and separated from the first gate electrode by a first gate dielectric layer, and a first source electrode coupled to the first channel layer. The second transistor includes a second gate electrode, a second channel layer including a second channel material and separated from the second gate electrode by a second gate dielectric layer, and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11348897B2

公开(公告)日：2022-05-31

申请号：US16647863

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Johanna M. Swan ,  Patrick Morrow ,  Kimin Jun ,  Brennen Mueller ,  Paul B. Fischer

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

公开(公告)号：US20220093725A1

公开(公告)日：2022-03-24

申请号：US17025209

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mohammad Enamul Kabir ,  Zhiguo Qian ,  Gerald S. Pasdast ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L49/02 ,  H01L23/49 ,  H01L23/492

Abstract: Disclosed herein are capacitors and resistors at direct bonding interfaces in microelectronic assemblies, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component, wherein a direct bonding interface of the second microelectronic component is direct bonded to a direct bonding interface of the first microelectronic component, the microelectronic assembly includes a sensor, the sensor includes a first sensor plate and a second sensor plate, the first sensor plate is at the direct bonding interface of the first microelectronic component, and the second sensor plate is at the direct bonding interface of the second microelectronic component.

公开(公告)号：US20220093492A1

公开(公告)日：2022-03-24

申请号：US17025771

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Krishna Bharath ,  Han Wui Then ,  Kimin Jun ,  Aleksandar Aleksov ,  Mohammad Enamul Kabir ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/49 ,  H05K1/11 ,  H01L23/538 ,  H01L23/532

Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.

公开(公告)号：US20200212011A1

公开(公告)日：2020-07-02

申请号：US16633543

申请日：2017-09-25

Applicant: INTEL CORPORATION

Inventor： Anup Pancholi ,  Kimin Jun

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L25/00

Abstract: An apparatus is provided which comprises: a first die having a first surface and a second surface, the first die comprising: a first layer formed on the first surface of the first die, and a second layer formed on the second surface of the first die; a second die coupled to the first layer; and a plurality of structures to couple the apparatus to an external component, wherein the plurality of structures is coupled to the second layer.