公开(公告)号：US10452397B2

公开(公告)日：2019-10-22

申请号：US15477022

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Abhishek R. Appu ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu

IPC: G06F9/30 ,  G06F12/0842 ,  G09G5/393 ,  G06T1/60 ,  G06T1/20 ,  G06F9/50

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to determine a first number of threads to be scheduled for each context of a plurality of contexts in a multi-context processing system, allocate a second number of streaming multiprocessors (SMs) to the respective plurality of contexts, and dispatch threads from the plurality of contexts only to the streaming multiprocessor(s) allocated to the respective plurality of contexts. Other embodiments are also disclosed and claimed.

公开(公告)号：US10403024B2

公开(公告)日：2019-09-03

申请号：US15988157

申请日：2018-05-24

Applicant: Intel Corporation

Inventor： Bimal Poddar ,  Prasoonkumar Surti ,  Rahul P. Sathe

IPC: G06T15/00 ,  G06T1/60 ,  G06T15/04 ,  G06T15/50 ,  G06T19/20

Abstract: Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.

公开(公告)号：US20190265765A1

公开(公告)日：2019-08-29

申请号：US16286166

申请日：2019-02-26

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Prasoonkumar Surti ,  Kiran C. Veernapu

IPC: G06F1/20 ,  G05B19/05

Abstract: Methods and apparatus relating to techniques for dynamic control of liquid cooling pumps to provide thermal cooling uniformity are described. In an embodiment, modification is made to operation of one or more of: one or more cooling pumps or one or more fans, based at least in part on comparison of one or more detected temperature or noise values at one or more components of a processor with one or more corresponding threshold values. The processor may include the logic that causes the modification and one or more sensors. The sensors are thermally or acoustically coupled to the one or more components of the processor to determine the detected temperature or noise values. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190251033A1

公开(公告)日：2019-08-15

申请号：US16277114

申请日：2019-02-15

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Prasoonkumar Surti ,  Kamal Sinha ,  Kiran C. Veernapu ,  Balaji Vembu

IPC: G06F12/0888 ,  G06F13/40 ,  G06T1/60 ,  G06T1/20 ,  G06F13/42

CPC classification number: G06F12/0888 ,  G06F12/0895 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2213/0026 ,  G06T1/20 ,  G06T1/60

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive, in a read/modify/write (RMW) pipeline, a cache access request from a requestor, wherein the cache request comprises a cache set identifier associated with requested data in the cache set, determine whether the cache set associated with the cache set identifier is in an inaccessible invalid state, and in response to a determination that the cache set is in an inaccessible state or an invalid state, to terminate the cache access request. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190236026A1

公开(公告)日：2019-08-01

申请号：US16287781

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Kiran C. Veernapu

IPC: G06F12/1045 ,  G06T1/20 ,  G06T1/60 ,  G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1063 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/455 ,  G06F2212/657 ,  G06F2212/68 ,  G06T1/20 ,  G06T1/60

Abstract: One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline to bypass a memory access for the first virtual page based on the first page table entry, wherein the graphics pipeline is to read a field in the first page table entry to determine a value of the clear color.

公开(公告)号：US20190206090A1

公开(公告)日：2019-07-04

申请号：US15859408

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Ben Ashbaugh ,  Prasoonkumar Surti ,  Pradeep Ramani ,  Rama Harihara ,  Jerin C. Justin ,  Jing Huang ,  Xiaoming Cui ,  Timothy B. Costa ,  Ting Gong ,  Elmoustapha Ould-Ahmed-Vall ,  Kumar Balasubramanian ,  Anil Thomas ,  Oguz H. Elibol ,  Jayaram Bobba ,  Guozhong Zhuang ,  Bhavani Subramanian ,  Gokce Keskin ,  Chandrasekaran Sakthivel ,  Rajesh Poornachandran

IPC: G06T9/00 ,  G06T15/00

CPC classification number: G06T9/002 ,  G06F12/023 ,  G06F2212/302 ,  G06F2212/401 ,  G06T15/005

Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.

公开(公告)号：US10332320B2

公开(公告)日：2019-06-25

申请号：US15488914

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Barath Lakshamanan ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Elmoustapha Ould-Ahmed-Vall ,  Liwei Ma ,  Jingyi Jin ,  Justin E. Gottschlich ,  Chandrasekaran Sakthivel ,  Michael S. Strickland ,  Brian T. Lewis ,  Lindsey Kuper ,  Altug Koker ,  Abhishek R. Appu ,  Prasoonkumar Surti ,  Joydeep Ray ,  Balaji Vembu ,  Javier S. Turek ,  Naila Farooqui

IPC: G01C22/00 ,  G07C5/00 ,  G05D1/00 ,  G01C21/34 ,  G08G1/01 ,  H04W28/08 ,  G06N20/00 ,  G06F9/50 ,  G08G1/052 ,  G01S19/13 ,  G05D1/02 ,  H04L29/08 ,  H04L12/26

Abstract: One embodiment provides for a computing device within an autonomous vehicle, the compute device comprising a wireless network device to enable a wireless data connection with an autonomous vehicle network, a set of multiple processors including a general-purpose processor and a general-purpose graphics processor, the set of multiple processors to execute a compute manager to manage execution of compute workloads associated with the autonomous vehicle, the compute workload associated with autonomous operations of the autonomous vehicle, and offload logic configured to execute on the set of multiple processors, the offload logic to determine to offload one or more of the compute workloads to one or more autonomous vehicles within range of the wireless network device.

公开(公告)号：US20190147640A1

公开(公告)日：2019-05-16

申请号：US16173722

申请日：2018-10-29

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer KP ,  Jonathan Kennedy ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Tomer Bar-On ,  Carsten Benthin ,  Adam T. Lake ,  Vasanth Ranganathan ,  Abhishek R. Appu

IPC: G06T15/08 ,  H04N5/369 ,  G06T15/00 ,  G06T15/60 ,  G06T15/10 ,  H04N5/232 ,  H04N13/239 ,  H04N13/344 ,  G06K9/00 ,  G02B27/01

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

公开(公告)号：US20190096024A1

公开(公告)日：2019-03-28

申请号：US15716280

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Altug Koker ,  Vasanth Ranganathan

IPC: G06T1/20 ,  G06F12/0875 ,  G06F12/1045 ,  G06F9/30 ,  G06T1/60 ,  G06T15/00

Abstract: Embodiments are generally directed to area-efficient implementations of graphics instructions. An embodiment of an apparatus includes a graphics subsystem, the graphics subsystem including one or more of a first logic for processing of memory read-return data for single-instruction-multiple-data instructions, the first logic to store data for a message in raw data format and delay conversion into shader format until all cache line requests for the message have been received; a second logic for assembly of memory read-return data for media block instructions into shader register format, the logic to provide for storage of valid bytes from a cache fragment in a register; or a third logic to remap scatter or gather instructions to untyped surface instruction types. An embodiment of an apparatus includes a graphics subsystem, the graphics subsystem including a translation lookaside buffer (TLB) and a data port controller to control the TLB, the data port controller including an incoming request pipeline to receive an incoming request with virtual address and generate a response, an incoming response pipeline to receive the response and generate a cache request, and an invalidation flow pipeline.

公开(公告)号：US10134115B2

公开(公告)日：2018-11-20

申请号：US15488619

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Prasoonkumar Surti ,  Joydeep Ray ,  Michael J. Norris

IPC: G06T15/00 ,  G06T5/00 ,  G06T1/20 ,  G06T1/60 ,  G06T11/00

Abstract: One embodiment provides for a general-purpose graphics processor comprising a fragment processing unit configured to generate pixel color data in a graphics processing pipeline, the fragment processing unit output color data to a multisample render target; and a memory allocator to allocate memory to store color data associated with the multisample render target, the memory allocator to merge a memory allocation for multiple pixels having a sample associated with equal color data.