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    Semiconductor memory device
    81.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07269087B2

    公开(公告)日：2007-09-11

    申请号：US11151417

    申请日：2005-06-14

    申请人： Masatoshi Hasegawa ,  Kazuhiko Kajigaya

    发明人： Masatoshi Hasegawa ,  Kazuhiko Kajigaya

    IPC分类号： G11C8/00

    CPC分类号： G11C29/808 ,  G11C7/18 ,  G11C11/4097 ,  G11C29/02 ,  G11C29/025 ,  G11C29/72 ,  G11C29/80 ,  G11C29/848

    摘要： In a bit-line direction, a plurality of memory mats are arranged including a plurality of memory cells respectively coupled to bit lines and word lines, and a sense amplifier array is arranged including a plurality of latch circuits having input/output nodes connected to a half of bit-line pairs separately provided to the memory mats in a region between the memory mats placed in the bit-line direction, thereby making possible to replace with a redundant bit line pair and the corresponding redundant sense amplifier on a basis of each bit-line pair and sense amplifier connected thereto, thereby realizing effective and rational Y-system relief.

    摘要翻译： 在位线方向上，多个存储器阵列被布置成包括分别耦合到位线和字线的多个存储器单元，并且读出放大器阵列被布置成包括多个锁存电路，其中输入/输出节点连接到 一半的位线对分别提供给放置在位线方向上的存储器垫之间的区域中的存储器堆，从而可以基于每个位替换冗余位线对和相应的冗余读出放大器 线对和读出放大器，从而实现有效和合理的Y系统释放。

    Semiconductor Device
    83.
    发明申请
    Semiconductor Device 有权
    半导体器件

    公开(公告)号：US20070147160A1

    公开(公告)日：2007-06-28

    申请号：US11467793

    申请日：2006-08-28

    申请人： Satoru Hanzawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Kazuhiko Kajigaya

    发明人： Satoru Hanzawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Kazuhiko Kajigaya

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1027 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/028 ,  G11C2207/002

    摘要： A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.

    摘要翻译： 提供了一种列电路，其将从读出放大器阵列SAA读取的信号放大到子放大器SAMP中的本地输入/输出线LIO，以将放大的信号传送到主输入/输出线MIO。 在每个子放大器SAMP中设置有能够根据读使能信号RD1，RD2设定两种电流之一的电流控制电路IC。 在定时控制器的控制下，在与脉冲串读取操作中的周期数相对应的定时，生成读使能信号RD 1，RD 2。 电流控制电路IC中的电流在刚刚激活存储体之后的脉冲串读取操作周期中的RD 1被设置为较大，而当前控制电路IC中的电流被下一个的RD 2设置得较小时， 随后的突发读取周期。 因此，可以在包括诸如DRAM的半导体存储器的半导体器件中实现操作余量的扩大或功率消耗的降低。

    Semiconductor device
    86.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20060193160A1

    公开(公告)日：2006-08-31

    申请号：US11354131

    申请日：2006-02-15

    申请人： Satoru Hanzawa ,  Riichiro Takemura ,  Kazuhiko Kajigaya

    发明人： Satoru Hanzawa ,  Riichiro Takemura ,  Kazuhiko Kajigaya

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04 ,  G11C15/043

    摘要： Control clocks of different phases are distributed to a memory array divided into multiple banks, and processing of entries and search keys (read and write operations and search operation) is performed at different phases. The memory array divided into banks is further divided into smaller arrays, that is, sub-arrays, and a sense amplifier in a read-write-search circuit block is shared by the two sub-arrays. In this case, a so-called open bit line structure in which each one bit line is connected from both sub-arrays to a sense amplifier is adopted. The same look-up table is registered to multiple banks, successively inputted search keys are sequentially inputted to the multiple banks, and the search operation is carried out in synchronization with the control clocks of different phases.

    摘要翻译： 将不同相位的控制时钟分配到划分为多个存储体的存储器阵列，并且在不同阶段执行条目和搜索关键字的处理（读取和写入操作和搜索操作）。 划分为存储体的存储器阵列进一步分成较小的阵列，即子阵列，并且读写搜索电路块中的读出放大器由两个子阵列共享。 在这种情况下，采用所谓的开放位线结构，其中每个位线都从两个子阵列连接到读出放大器。 相同的查找表被注册到多个存储体，连续输入的搜索键被顺序地输入到多个存储体，并且与不同相位的控制时钟同步地执行搜索操作。

    Semiconductor integrated circuit
    87.
    发明申请
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US20060108640A1

    公开(公告)日：2006-05-25

    申请号：US11281743

    申请日：2005-11-18

    申请人： Kazuhiko Kajigaya ,  Kanji Otsuka

    发明人： Kazuhiko Kajigaya ,  Kanji Otsuka

    IPC分类号： H01L29/94

    CPC分类号： G11C7/1051 ,  G11C7/1057 ,  H01L27/092

    摘要： A semiconductor integrated circuit comprising: a pair of MOS transistors which are formed in a same well on a semiconductor substrate and arranged adjacent to each other with a distance such that charge exchange between capacitances of respective drain diffusion layers is possible; and a wiring structure which is formed to apply differential signals to respective gates of the pair of MOS transistors and to apply a common potential to respective sources of the pair of MOS transistors.

    摘要翻译： 一种半导体集成电路，包括：一对MOS晶体管，其形成在半导体衬底上的相同阱中并且彼此相邻布置，使得可以使各个漏极扩散层的电容之间的电荷交换成为可能; 以及布线结构，其被形成为将差分信号施加到所述一对MOS晶体管的各个栅极，并向所述一对MOS晶体管的各个源施加公共电位。

    Semiconductor memory device
    88.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06992343B2

    公开(公告)日：2006-01-31

    申请号：US10975494

    申请日：2004-10-29

    申请人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

    发明人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/108 ,  G11C7/18 ,  G11C11/403 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10897 ,  Y10S257/905 ,  Y10S257/906

    摘要： A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.

    摘要翻译： 提供一种半导体存储器件，其可以通过减少存储器单元的面积的增加并获得超宽带的周期来实现信息保持时间期间的高集成度，超高速度运行和功耗的显着降低， 高速读出时间，确保自刷新时间长的刷新周期。 采用单交点单元两个单元/比特方法的DRAM具有采用单交叉6F 单元的双单元结构，其结构是：将存储单元布置在与 位线对和字线之间的交点; 并且当字线的半间距被定义为F时，位线对的每个位线的间距大于2F且小于4F。 此外，在硅衬底中形成每个存储单元的晶体管的源极，沟道和漏极的有源区相对于位线对的方向倾斜地形成。

    Semiconductor memory device
    89.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20050232038A1

    公开(公告)日：2005-10-20

    申请号：US11151417

    申请日：2005-06-14

    申请人： Masatoshi Hasegawa ,  Kazuhiko Kajigaya

    发明人： Masatoshi Hasegawa ,  Kazuhiko Kajigaya

    IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04

    CPC分类号： G11C29/808 ,  G11C7/18 ,  G11C11/4097 ,  G11C29/02 ,  G11C29/025 ,  G11C29/72 ,  G11C29/80 ,  G11C29/848

    摘要： In a bit-line direction, a plurality of memory mats are arranged including a plurality of memory cells respectively coupled to bit lines and word lines, and a sense amplifier array is arranged including a plurality of latch circuits having input/output nodes connected to a half of bit-line pairs separately provided to the memory mats in a region between the memory mats placed in the bit-line direction, thereby making possible to replace with a redundant bit line pair and the corresponding redundant sense amplifier on a basis of each bit-line pair and sense amplifier connected thereto, thereby realizing effective and rational Y-system relief.

    摘要翻译： 在位线方向上，多个存储器阵列被布置成包括分别耦合到位线和字线的多个存储器单元，并且读出放大器阵列被布置成包括多个锁存电路，其中输入/输出节点连接到 一半的位线对分别提供给放置在位线方向上的存储器垫之间的区域中的存储器堆，从而可以基于每个位替换冗余位线对和相应的冗余读出放大器 线对和读出放大器，从而实现有效和合理的Y系统释放。