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    Shielded gate trench FET with multiple channels
    83.
    发明授权
    Shielded gate trench FET with multiple channels 有权
    多通道屏蔽栅沟槽FET

    公开(公告)号：US09224853B2

    公开(公告)日：2015-12-29

    申请号：US13553285

    申请日：2012-07-19

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423

    CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7831

    Abstract: In one embodiment, an apparatus can include a trench extending into a semiconductor region of a first conductivity type, an electrode disposed in the trench, and a source region of the first conductivity type abutting a sidewall of the trench. The apparatus can include a first well region of a second conductivity type disposed in the semiconductor region below the source region and abutting the sidewall of the trench lateral to the electrode where the second conductivity type is opposite the first conductivity type. The apparatus can also include a second well region of the second conductivity type disposed in the semiconductor region and abutting the sidewall of the trench, and a third well region of the first conductivity type disposed between the first well region and the second well region.

    Abstract translation: 在一个实施例中，装置可以包括延伸到第一导电类型的半导体区域中的沟槽，设置在沟槽中的电极以及与沟槽的侧壁邻接的第一导电类型的源极区域。 该装置可以包括设置在源极区域下方的半导体区域中的第二导电类型的第一阱区域，并且与第二导电类型与第一导电类型相反的电极的横向侧壁邻接沟槽的侧壁。 该装置还可以包括设置在半导体区域中并邻接沟槽的侧壁的第二导电类型的第二阱区域以及布置在第一阱区域和第二阱区域之间的第一导电类型的第三阱区域。

    Technique for controlling trench profile in semiconductor structures
    84.
    发明授权
    Technique for controlling trench profile in semiconductor structures 有权
    用于控制半导体结构中的沟槽轮廓的技术

    公开(公告)号：US08815744B2

    公开(公告)日：2014-08-26

    申请号：US12109302

    申请日：2008-04-24

    Applicant: Hui Chen ,  Qi Wang ,  Briant Harward ,  James Pan

    Inventor： Hui Chen ,  Qi Wang ,  Briant Harward ,  James Pan

    IPC: H01L21/311

    CPC classification number: H01L21/3065 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

    Abstract: A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.

    Abstract translation: 一种形成半导体结构的方法包括以下步骤。 在半导体区域中使用掩模层形成沟槽，使得沟槽具有第一深度，沿其底部的第一宽度和具有第一斜率的侧壁。 去除掩模层，并且执行斜面蚀刻以使沟槽的侧壁逐渐变细，使得侧壁具有小于第一斜率的第二斜率。

    Management of requested or pushed content in communications client devices
    85.
    发明授权
    Management of requested or pushed content in communications client devices 有权
    管理通信客户端设备中的请求或推送内容

    公开(公告)号：US08805775B1

    公开(公告)日：2014-08-12

    申请号：US11249554

    申请日：2005-10-13

    Applicant: James Pan ,  Claudio Lima ,  James Black

    Inventor： James Pan ,  Claudio Lima ,  James Black

    IPC: G06F17/00 ,  G06F7/00

    CPC classification number: G06F17/30902

    Abstract: A system, a method and computer-readable media for managing content received over a network by a client device. A network transmission communicating an item of content is detected by a client device, and a determination is made whether the client device is in a mode of operation that allows the storing of uninvited media content. For example, the client device may be a mobile communication device monitoring the media being transmitted over a broadcast channel. When an item of content is observed traversing the broadcast channel, a set of user-defined preferences is accessed to determine whether to permit receiving the item. If permitted, the item of content is stored in a data store on the client device for subsequent presentation to the user.

    Abstract translation: 一种用于管理由客户端设备通过网络接收的内容的系统，方法和计算机可读介质。 通过客户端装置检测传送内容的网络传输，并且确定客户端装置是否处于允许存储未邀请的媒体内容的操作模式。 例如，客户端设备可以是监视通过广播信道发送的媒体的移动通信设备。 当通过广播频道观察内容项目时，访问一组用户定义的偏好以确定是否允许接收该项目。 如果允许的话，内容项被存储在客户端设备上的数据存储器中，以供随后呈现给用户。

    UCP4
    88.
    发明申请
    UCP4 有权

    公开(公告)号：US20120041176A1

    公开(公告)日：2012-02-16

    申请号：US13236459

    申请日：2011-09-19

    Applicant: Sean Adams ,  James Pan ,  Alan Zhong

    Inventor： Sean Adams ,  James Pan ,  Alan Zhong

    IPC: C07K14/435 ,  C12P21/06

    CPC classification number: C07K14/4702 ,  A61K38/00 ,  A61K48/00 ,  C07K14/47 ,  C07K2319/00

    Abstract: The present invention is directed to novel polypeptides having homology to certain human uncoupling proteins (“UCPs”) and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention, and methods for producing the polypeptides of the present invention.

    Abstract translation: 本发明涉及与某些人解偶联蛋白（“UCP”）和编码那些多肽的核酸分子具有同源性的新型多肽。 本文还提供了包含那些核酸序列的载体和宿主细胞，包含与异源多肽序列融合的本发明多肽的嵌合多肽分子，与本发明的多肽结合的抗体，以及本发明多肽的制备方法 发明。

    Resonant cavity complementary optoelectronic transistors
    89.
    发明授权
    Resonant cavity complementary optoelectronic transistors 有权
    谐振腔互补光电晶体管

    公开(公告)号：US08084795B2

    公开(公告)日：2011-12-27

    申请号：US12470566

    申请日：2009-05-22

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01S5/00 ,  H01L33/00

    CPC classification number: H01S5/0261 ,  H01L27/15 ,  H01S5/0262

    Abstract: The CMOS field effect transistors, used in microprocessors and other digital VLSI circuits, face major challenges such as thin gate dielectrics leakage and scaling limits, severe short channel effects, limited performance improvement with scaling, complicated fabrication process with added special techniques, and surface mobility degradation. This disclosure proposes a new CMOS-compatible optoelectronic transistor. The current is much higher than the MOS transistors, due to the high carrier mobility with bulk transportation. The optoelectronic transistors are scalable to the sub-nanometer ranges without short channel effects. It is also suitable for low power applications and ULSI circuits. The new transistor consists of a laser or LED diode as drain or source, and a photo sensor diode (avalanche photo diode) as source or drain. The transistor is turned on by applying a gate voltage, similar to the CMOS transistors, and a laser or LED light signal is sent to the nearby photo diode, causing an avalanche breakdown and high drain current. The transistor is surrounded by dielectrics and metal isolations, which serve as a metal box or cavity, so the generated laser or LED lights are confined and reflected back from the metal. The drain current increases exponentially with the drain or gate voltage. This exponential drain current vs. drain or gate voltage characteristics makes the optoelectronic transistor run much faster than the transitional linear MOSFET.The optic transistor current-voltage characteristics are totally different from transitional CMOS transistors.

    Abstract translation: 在微处理器和其他数字VLSI电路中使用的CMOS场效应晶体管面临诸如薄栅极电介质泄漏和结垢限制，严重的短沟道效应，缩放的有限性能改进，附加特殊技术的复杂制造工艺和表面迁移率等主要挑战 降解。 本公开提出了一种新的兼容CMOS的光电晶体管。 电流远高于MOS晶体管，这是由于大容量运输的高载流子迁移率。 光电子晶体管可以扩展到亚纳米范围，而没有短信道效应。 它也适用于低功率应用和ULSI电路。 新的晶体管由激光器或LED二极管作为漏极或源极，以及作为源极或漏极的光电二极管（雪崩光电二极管）组成。 通过施加类似于CMOS晶体管的栅极电压来接通晶体管，并且将激光或LED光信号发送到附近的光电二极管，导致雪崩击穿和高漏极电流。 晶体管被电介质和金属隔离物所围绕，它们用作金属盒或空腔，因此产生的激光或LED灯被限制并从金属反射回来。 漏极电流随漏极或栅极电压呈指数增长。 该指数漏极电流与漏极或栅极电压特性使得光电晶体管的运行比过渡线性MOSFET快得多。 光晶体管电流 - 电压特性与过渡CMOS晶体管完全不同。

    Replacement metal gate transistors with reduced gate oxide leakage
    90.
    发明授权
    Replacement metal gate transistors with reduced gate oxide leakage 有权
    替代金属栅极晶体管，栅极氧化物泄漏减少

    公开(公告)号：US08053849B2

    公开(公告)日：2011-11-08

    申请号：US11269745

    申请日：2005-11-09

    Applicant: James Pan ,  John Pellerin

    Inventor： James Pan ,  John Pellerin

    IPC: H01L21/02

    CPC classification number: H01L21/28008 ,  H01L21/28088 ,  H01L21/28238 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    Abstract: Thin effective gate oxide thickness with reduced leakage for replacement metal gate transistors is achieved by forming a protective layer between the gate oxide layer and metal gate electrode, thereby reducing stress. Embodiments include forming a protective layer of amorphous carbon containing metal carbides decreasing in concentration from the metal gate electrode toward the gate oxide layer across the protective layer. Embodiments of methodology include removing the removable gate, depositing a layer of amorphous carbon on the gate oxide layer, forming the metal gate electrode and then heating at an elevated temperature to diffuse metal from the metal gate electrode into the amorphous carbon layer, thereby forming the metal carbides. Embodiments also include metal gate transistors with a gate oxide layer having a high dielectric constant and silicon concentrated at the interfaces with the metal gate electrode and substrate.

    Abstract translation: 通过在栅极氧化层和金属栅电极之间形成保护层来实现用于替换金属栅极晶体管的具有减小的泄漏的薄的有效栅极氧化物厚度，从而降低应力。 实施例包括形成从金属栅电极朝向保护层的栅极氧化物层浓缩的含有金属碳化物的非晶碳保护层。 方法的实施例包括去除可移除栅极，在栅极氧化物层上沉积无定形碳层，形成金属栅电极，然后在升高的温度下加热以使金属从金属栅电极扩散到无定形碳层中，从而形成 金属碳化物。 实施例还包括具有高介电常数的栅极氧化物层和在与金属栅电极和衬底的界面处集中的硅的金属栅极晶体管。

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