公开(公告)号：US20070049004A1

公开(公告)日：2007-03-01

申请号：US11591017

申请日：2006-10-31

申请人： John Smythe

发明人： John Smythe

IPC分类号： H01L21/4763

CPC分类号： H01L21/02126 ,  H01L21/02211 ,  H01L21/02222 ,  H01L21/288 ,  H01L21/316 ,  H01L21/32051 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877

摘要： The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise one or both of aluminum silane and aluminum silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.

摘要翻译： 本发明包括在与半导体衬底相关联的波状表面形貌上保形地形成层的方法。 起伏的表面形貌可以首先暴露于氧化钛，氧化钕，氧化钇，氧化锆和氧化钒中的一种或多种以处理表面，并且随后可以暴露于沿着被处理的表面共形形成层的材料。 该材料可以例如包括铝硅烷和铝硅氮烷中的一种或两种。 本发明还包括在包含氧化钛，氧化钇，氧化锆和氧化钒中的一种或多种的衬垫上形成保形层的半导体结构。

公开(公告)号：US20060125043A1

公开(公告)日：2006-06-15

申请号：US11009665

申请日：2004-12-10

申请人： John Smythe ,  William Budge

发明人： John Smythe ,  William Budge

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.

摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面中蚀刻沟槽之后，衬垫层优选沉积到沟槽中。 然后在沟槽上进行各向异性等离子体处理。 在等离子体工艺期间，硅层可以沉积在沟槽的基底上，或等离子体可以处理衬层。 然后用旋涂前体填充沟槽。 然后施加致密化或反应过程以将旋涂材料转化成绝缘体，并且氧化沟槽底部的富硅层。 所得到的沟槽具有从沟槽的顶部到底部的一致的蚀刻速率。

公开(公告)号：US20060102977A1

公开(公告)日：2006-05-18

申请号：US11321511

申请日：2005-12-29

申请人： Janos Fucsko ,  John Smythe ,  Li Li ,  Grady Waldo

发明人： Janos Fucsko ,  John Smythe ,  Li Li ,  Grady Waldo

IPC分类号： H01L29/00

CPC分类号： H01L21/02164 ,  H01L21/02222 ,  H01L21/02236 ,  H01L21/02282 ,  H01L21/02343 ,  H01L21/3125 ,  H01L21/316 ,  H01L21/76205 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832

摘要： Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.

公开(公告)号：US20060038293A1

公开(公告)日：2006-02-23

申请号：US10924707

申请日：2004-08-23

申请人： Neal Rueger ,  Chris Hill ,  Zailong Bian ,  John Smythe

发明人： Neal Rueger ,  Chris Hill ,  Zailong Bian ,  John Smythe

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L21/76837 ,  H01L21/76834 ,  H01L23/53223 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T29/49117 ,  H01L2924/00

摘要： An inter-metal dielectric (IMD) fill process includes depositing an insulating nanolaminate barrier layer. The nanolaminate is preferably an oxide liner formed by using an alternating layer deposition process. The layer is highly conformal and is an excellent diffusion barrier. Gaps between metal lines are filled using high density plasma chemical vapor deposition with a reactive species gas. The barrier layer protects the metal lines from shorts between neighboring layers. The resulting structure has substantially uneroded metal lines and an insulating IMD fill.

摘要翻译： 金属间电介质（IMD）填充工艺包括沉积绝缘的纳米层间隔离层。 纳米酸盐优选是通过使用交替层沉积工艺形成的氧化物衬垫。 该层是高度保形的，是一个很好的扩散屏障。 使用具有反应性物质气体的高密度等离子体化学气相沉积来填充金属线之间的间隙。 阻挡层保护金属线免受相邻层之间的短路。 所得到的结构具有基本上未编码的金属线和绝缘IMD填充物。

公开(公告)号：US20050186755A1

公开(公告)日：2005-08-25

申请号：US10782997

申请日：2004-02-19

申请人： John Smythe ,  Jigish Trivedi

发明人： John Smythe ,  Jigish Trivedi

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.

摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面中蚀刻沟槽之后，将氧势垒沉积到沟槽中。 然后沉积可膨胀的可氧化衬垫，优选非晶硅。 然后用旋涂电介质（SOD）材料填充沟槽。 然后施加致密化过程，由此SOD材料收缩并且可氧化衬里膨胀。 优选地，在致密化过程的至少部分期间，温度升高而氧化。 所形成的沟槽具有可忽略的垂直湿蚀刻速率梯度和在沟槽顶部的可忽略的凹陷。

公开(公告)号：US09577186B2

公开(公告)日：2017-02-21

申请号：US13488190

申请日：2012-06-04

申请人： Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

发明人： Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

IPC分类号： H01L21/00 ,  H01L45/00 ,  H01L27/24

CPC分类号： H01L45/04 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive state metal oxide-comprising material is formed over the first conductive electrode. Conductive material is deposited over the multi-resistive state metal oxide-comprising material. A second conductive electrode of the memory cell which comprises the conductive material is received over the multi-resistive state metal oxide-comprising material. The forming thereof includes etching through the conductive material to form opposing laterally outermost conductive edges of said conductive material in the one planar cross section at the conclusion of said etching which are received laterally outward of the opposing laterally outermost edges of the first conductive electrode in the one planar cross section.

摘要翻译： 形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。 第一导电电极在一个平面横截面中具有垂直最外表面和在最外表面处的相对的横向最外边缘。 在第一导电电极上形成包含多电阻态金属氧化物的材料。 导电材料沉积在多电阻状态的含金属氧化物的材料上。 包含导电材料的存储单元的第二导电电极被接收在多电阻状态的含金属氧化物的材料上。 其形成包括通过导电材料的蚀刻，以在所述蚀刻结束时在一个平面截面中形成所述导电材料的相对的横向最外面的导电边缘，其在第一导电电极的相对的横向最外边缘的横向外侧接收 一个平面截面。

公开(公告)号：US08963330B2

公开(公告)日：2015-02-24

申请号：US13401534

申请日：2012-02-21

申请人： John Smythe

发明人： John Smythe

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L21/288 ,  H01L21/316 ,  H01L21/3205

CPC分类号： H01L21/02126 ,  H01L21/02211 ,  H01L21/02222 ,  H01L21/288 ,  H01L21/316 ,  H01L21/32051 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877

摘要： The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise an aluminum-containing compound and one or both of silane and silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.

摘要翻译： 本发明包括在与半导体衬底相关联的波状表面形貌上保形地形成层的方法。 起伏的表面形貌可以首先暴露于氧化钛，氧化钕，氧化钇，氧化锆和氧化钒中的一种或多种以处理表面，并且随后可以暴露于沿着被处理的表面共形形成层的材料。 该材料可以例如包含含铝化合物和硅烷和硅氮烷中的一种或两种。 本发明还包括在包含氧化钛，氧化钇，氧化锆和氧化钒中的一种或多种的衬垫上形成保形层的半导体结构。

公开(公告)号：US08861179B2

公开(公告)日：2014-10-14

申请号：US13597708

申请日：2012-08-29

申请人： Rishikesh Krishnan ,  John Smythe ,  Vishwanath Bhat ,  Noel Rocklein ,  Bhaskar Srinivasan ,  Jeff Hull ,  Chris Carlson

发明人： Rishikesh Krishnan ,  John Smythe ,  Vishwanath Bhat ,  Noel Rocklein ,  Bhaskar Srinivasan ,  Jeff Hull ,  Chris Carlson

IPC分类号： H01G4/06 ,  H01G4/20 ,  H01G4/10

CPC分类号： H01L28/56 ,  H01G4/10 ,  H01L27/108

摘要： Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10−7 amps/cm2 at from −1.1V to +1.1V.

摘要翻译： 公开了形成电容器的电容器和方法，其包括内部导电金属电容器电极和外部导电金属电容器电极。 电容器电介质区域被容纳在内导电金属电容电极和外导电金属电容器电极之间，并且具有不大于150埃的厚度。 公开了厚度和关系的材料的各种组合，其相互之间可以实现和导致电介质区域的介电常数k至少为35，而在-1.1V至-1.0V的范围内漏电流不大于1×10-7Aps / + 1.1V。

公开(公告)号：US08557697B2

公开(公告)日：2013-10-15

申请号：US12893807

申请日：2010-09-29

申请人： Bhaskar Srinivasan ,  John Smythe

发明人： Bhaskar Srinivasan ,  John Smythe

IPC分类号： H01L21/4763

CPC分类号： C23C16/405 ,  C23C16/409 ,  C23C16/45529 ,  C23C16/45531 ,  H01G4/085 ,  H01G4/1227 ,  H01L21/02186 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31691

摘要： Atomic layer deposition methods as described herein can be advantageously used to form a metal-containing layer on a substrate. For example, certain methods as described herein can form a strontium titanate layer that has low carbon content (e.g., low strontium carbonate content), which can result in layer with a high dielectric constant.

摘要翻译： 本文所述的原子层沉积方法可有利地用于在基底上形成含金属的层。 例如，如本文所述的某些方法可以形成具有低碳含量（例如低碳酸锶含量）的钛酸锶层，其可导致具有高介电常数的层。

公开(公告)号：US08415661B2

公开(公告)日：2013-04-09

申请号：US13491165

申请日：2012-06-07

申请人： Neil Greeley ,  Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

发明人： Neil Greeley ,  Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

IPC分类号： H01L29/06

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1658 ,  H01L45/1683

摘要： Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

摘要翻译： 用于形成包含掺杂的硫族化物材料的存储器存取装置的自对准制造方法。 该方法可用于形成三维堆叠的交叉点存储器阵列。 该方法包括在第一导电电极上形成绝缘材料，图案化绝缘材料以形成暴露第一导电电极的部分的通孔，在绝缘材料的通孔内形成存储器访问装置，并在存储器访问上形成存储元件 设备，其中存储在所述存储器元件中的数据可经由所述存储器访问设备访问。 存储器存取装置由掺杂的硫族化物材料形成，并使用自对准制造方法形成。