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    MOM capacitor having local interconnect metal plates and related method
    82.
    发明授权
    MOM capacitor having local interconnect metal plates and related method 有权
    具有局部互连金属板的MOM电容器及相关方法

    公开(公告)号：US08890288B2

    公开(公告)日：2014-11-18

    申请号：US13270452

    申请日：2011-10-11

    申请人： Xiangdong Chen ,  Henry Kuo-Shun Chen

    发明人： Xiangdong Chen ,  Henry Kuo-Shun Chen

    IPC分类号： H01L21/02 ,  H01L23/522 ,  H01L27/06 ,  H01L49/02

    CPC分类号： H01L28/86 ,  H01L23/5223 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

    摘要： According to one exemplary embodiment, a metal-oxide-metal (MOM) capacitor in a semiconductor die comprises a first plurality of capacitor plates and a second plurality of capacitor plates sharing a plane parallel to and below a plane of a first metallization layer of the semiconductor die. The MOM capacitor further comprises a local interlayer dielectric between the first plurality of capacitor plates and the second plurality of capacitor plates. The first and second plurality of capacitor plates are made from a local interconnect metal for connecting devices formed in a device layer of the semiconductor die situated below the first metallization layer.

    摘要翻译： 根据一个示例性实施例，半导体管芯中的金属氧化物金属（MOM）电容器包括第一多个电容器板和第二多个电容器板，第二多个电容器板共享平行于第一金属化层 半导体芯片。 MOM电容器还包括在第一多个电容器板和第二多个电容器板之间的局部层间电介质。 第一和第二多个电容器板由局部互连金属制成，用于连接形成在位于第一金属化层下方的半导体管芯的器件层中的器件。

    Interposer structure with passive component and method for fabricating same
    83.
    发明授权
    Interposer structure with passive component and method for fabricating same 有权
    具有无源元件的内插器结构及其制造方法

    公开(公告)号：US08866258B2

    公开(公告)日：2014-10-21

    申请号：US12587482

    申请日：2009-10-06

    申请人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

    发明人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

    IPC分类号： H01L27/08 ,  H01L23/498 ,  H01L21/768 ,  H01L21/48 ,  H01L23/14

    CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/49822 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2924/15311

    摘要： According to an exemplary embodiment, an interposer structure for electrically coupling a semiconductor die to a support substrate in a semiconductor package includes at least one through-wafer via extending through a semiconductor substrate, where the at least one through-wafer via provides an electrical connection between the semiconductor die and the support substrate. The interposer structure further includes a passive component including a trench conductor, where the trench conductor extends through the semiconductor substrate. The passive component further includes a dielectric liner situated between the trench conductor and the semiconductor substrate. The passive component can further include at least one conductive pad for electrically coupling the trench conductor to the semiconductor die. The passive component can be, for example, an inductor or an antenna.

    摘要翻译： 根据示例性实施例，用于将半导体管芯电耦合到半导体封装中的支撑衬底的插入器结构包括延伸穿过半导体衬底的至少一个贯通晶片，其中至少一个贯通晶片通孔提供电连接 在半导体管芯和支撑衬底之间。 插入器结构还包括无源部件，其包括沟槽导体，其中沟槽导体延伸穿过半导体衬底。 无源部件还包括位于沟槽导体和半导体衬底之间的电介质衬垫。 无源部件还可以包括至少一个用于将沟槽导体电耦合到半导体管芯的导电焊盘。 无源部件可以是例如电感器或天线。

    Fin-based adjustable resistor
    84.
    发明授权
    Fin-based adjustable resistor 有权
    鳍式可调电阻

    公开(公告)号：US08836032B2

    公开(公告)日：2014-09-16

    申请号：US13277547

    申请日：2011-10-20

    申请人： Wei Xia ,  Xiangdong Chen

    发明人： Wei Xia ,  Xiangdong Chen

    IPC分类号： H01L27/12 ,  H01L29/78

    CPC分类号： H01L29/785 ,  H01L2029/7857

    摘要： According to one exemplary embodiment, a fin-based adjustable resistor includes a fin channel of a first conductivity type, and a gate surrounding the fin channel. The fin-based adjustable resistor also includes first and second terminals of the first conductivity type being contiguous with the fin channel, and being situated on opposite sides of the fin channel. The fin channel is lower doped relative to the first and second terminals. The resistance of the fin channel between the first and second terminals is adjusted by varying a voltage applied to the gate so as to achieve the fin-based adjustable resistor. The gate can be on at least two sides of the fin channel. Upon application of a depletion voltage, the fin channel can be depleted before an inversion is formed in the fin channel.

    摘要翻译： 根据一个示例性实施例，鳍状可调电阻器包括第一导电类型的鳍状沟道和围绕鳍状沟道的栅极。 鳍状可调电阻器还包括第一导电类型的第一和第二端子，其与鳍状通道邻接并位于翅片通道的相对侧上。 翅片通道相对于第一和第二端子较低掺杂。 通过改变施加到栅极的电压来调节第一和第二端子之间的鳍状通道的电阻，从而实现基于鳍片的可调电阻器。 门可以在鳍通道的至少两侧。 在施加耗尽电压时，在鳍式通道中形成反转之前，可以耗尽鳍通道。

    Semiconductor package having an interposer configured for magnetic signaling
    85.
    发明授权
    Semiconductor package having an interposer configured for magnetic signaling 有权
    具有配置用于磁信令的插入器的半导体封装

    公开(公告)号：US08791533B2

    公开(公告)日：2014-07-29

    申请号：US13361598

    申请日：2012-01-30

    申请人： Xiangdong Chen ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp

    发明人： Xiangdong Chen ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp

    IPC分类号： H01L29/82

    CPC分类号： H01L23/48 ,  H01L23/49827 ,  H01L25/0655 ,  H01L2225/06531 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There are disclosed herein various implementations of semiconductor packages having an interposer configured for magnetic signaling. One exemplary implementation includes a die transmit pad in an active die for transmitting a magnetic signal corresponding to a die electrical signal produced by the active die, and an interposer magnetic tunnel junction (MTJ) pad in the interposer for receiving the magnetic signal. A sensing circuit is coupled to the interposer MTJ pad for producing a receive electrical signal corresponding to the magnetic signal. In one implementation, the sensing circuit is configured to sense a resistance of the interposer MTJ pad and to produce the receive electrical signal according to the sensed resistance.

    摘要翻译： 这里公开了具有配置用于磁信令的插入器的半导体封装的各种实施方式。 一个示例性实施例包括用于传输对应于由有源管芯产生的管芯电信号的磁信号的有源管芯中的管芯发射焊盘以及用于接收磁信号的插入器磁隧道结（MTJ）焊盘。 感测电路耦合到插入器MTJ焊盘，用于产生对应于磁信号的接收电信号。 在一个实现中，感测电路被配置为感测插入器MTJ焊盘的电阻并且根据所感测的电阻产生接收电信号。

    Semiconductor Package Having an Interposer Configured for Magnetic Signaling
    87.
    发明申请
    Semiconductor Package Having an Interposer Configured for Magnetic Signaling 有权
    具有配置用于磁信号的插入器的半导体封装

    公开(公告)号：US20130193587A1

    公开(公告)日：2013-08-01

    申请号：US13361598

    申请日：2012-01-30

    申请人： Xiangdong Chen ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp

    发明人： Xiangdong Chen ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp

    IPC分类号： H01L23/52

    CPC分类号： H01L23/48 ,  H01L23/49827 ,  H01L25/0655 ,  H01L2225/06531 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There are disclosed herein various implementations of semiconductor packages having an interposer configured for magnetic signaling. One exemplary implementation includes a die transmit pad in an active die for transmitting a magnetic signal corresponding to a die electrical signal produced by the active die, and an interposer magnetic tunnel junction (MTJ) pad in the interposer for receiving the magnetic signal. A sensing circuit is coupled to the interposer MTJ pad for producing a receive electrical signal corresponding to the magnetic signal. In one implementation, the sensing circuit is configured to sense a resistance of the interposer MTJ pad and to produce the receive electrical signal according to the sensed resistance.

    摘要翻译： 这里公开了具有配置用于磁信令的插入器的半导体封装的各种实施方式。 一个示例性实施例包括用于传输对应于由有源管芯产生的管芯电信号的磁信号的有源管芯中的管芯发射焊盘，以及用于接收磁信号的插入器磁隧道结（MTJ）焊盘。 感测电路耦合到插入器MTJ焊盘，用于产生对应于磁信号的接收电信号。 在一个实现中，感测电路被配置为感测插入器MTJ焊盘的电阻并且根据所感测的电阻产生接收电信号。

    Semiconductor Package with Ultra-Thin Interposer Without Through-Semiconductor Vias
    88.
    发明申请
    Semiconductor Package with Ultra-Thin Interposer Without Through-Semiconductor Vias 有权
    具有超薄型内插器的半导体封装，没有直通半导体通孔

    公开(公告)号：US20130168860A1

    公开(公告)日：2013-07-04

    申请号：US13339234

    申请日：2011-12-28

    申请人： Sampath K.V. Karikalan ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

    发明人： Sampath K.V. Karikalan ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

    IPC分类号： H01L23/538 ,  H01L23/532

    CPC分类号： H01L23/538 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5223 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311

    摘要： There are disclosed herein various implementations of semiconductor packages including an interposer without through-semiconductor vias (TSVs). One exemplary implementation includes a first active die situated over an interposer. The interposer includes an interposer dielectric having intra-interposer routing traces. The first active die communicates electrical signals to a package substrate situated below the interposer utilizing the intra-interposer routing traces and without utilizing TSVs. In one implementation, the semiconductor package includes a second active die situated over the interposer, the second active die communicating electrical signals to the package substrate utilizing the intra-interposer routing traces and without utilizing TSVs. Moreover, in one implementation, the first active die and the second active die communicate chip-to-chip signals through the interposer.

    摘要翻译： 这里公开了包括没有半导体通孔（TSV）的插入器的半导体封装的各种实施方式。 一个示例性实施方式包括位于中介层之上的第一有源裸片。 插入器包括具有内插器布线迹线的中介层电介质。 第一有源管芯将电信号传送到位于插入器下方的封装衬底，利用内插器布线迹线并且不使用TSV。 在一个实施方案中，半导体封装包括位于插入器上方的第二有源裸片，第二有源裸片利用内插器布线迹线将电信号传送到封装衬底，并且不使用TSV。 此外，在一个实现中，第一有源管芯和第二有源管芯通过插入器传送芯片到芯片信号。

    Zener Diode Structure and Process
    90.
    发明申请
    Zener Diode Structure and Process 有权
    齐纳二极管结构与工艺

    公开(公告)号：US20130082330A1

    公开(公告)日：2013-04-04

    申请号：US13250563

    申请日：2011-09-30

    申请人： Wei Xia ,  Xiangdong Chen

    发明人： Wei Xia ,  Xiangdong Chen

    IPC分类号： H01L27/092 ,  H01L21/60 ,  H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L24/13 ,  H01L24/14 ,  H01L27/0629 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2924/12035 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

    摘要： A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

    摘要翻译： 垂直堆叠的平面结齐纳二极管与外延生长的FET升高的S / D端子同时形成。 齐纳二极管的结构和工艺与Gate-Last高k FET结构和工艺兼容。 二极管和晶体管结构的横向分离由改进的STI屏蔽提供。 不需要额外的光刻步骤。 在一些实施例中，最上面的二极管端子的非结面用镍硅化，以另外作为铜扩散阻挡层。