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    ALMOST READY MEMORY MANAGMENT
    81.
    发明申请
    ALMOST READY MEMORY MANAGMENT 有权

    公开(公告)号：US20220328109A1

    公开(公告)日：2022-10-13

    申请号：US17229476

    申请日：2021-04-13

    Applicant: Micron Technology, Inc.

    Inventor： Yoav Weinberg ,  Eric N. Lee

    IPC: G11C16/34 ,  G11C16/20 ,  G11C16/26 ,  G11C16/32 ,  G11C7/10

    Abstract: A method includes determining, via status polling at a first interval, an indicator of an almost ready status of a set of memory cells of a memory device, based on the indicator of the almost ready status, determining the set of memory cells of the memory device is almost ready to complete execution of an operation on the set of memory cells of the memory device, and responsive to determining the set of memory cells of the memory device is almost ready to complete execution of the operation, performing status polling at a second interval.

    Intervallic dynamic start voltage and program verify sampling in a memory sub-system
    82.
    发明授权
    Intervallic dynamic start voltage and program verify sampling in a memory sub-system 有权

    公开(公告)号：US11462281B1

    公开(公告)日：2022-10-04

    申请号：US17307443

    申请日：2021-05-04

    Applicant: Micron Technology, Inc.

    Inventor： Lawrence Celso Miranda ,  Eric N. Lee ,  Tong Liu ,  Sheyang Ning ,  Cobie B. Loper ,  Ugo Russo

    IPC: G11C16/12 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/06

    Abstract: Control logic in a memory device identifies a first group of wordlines associated with a first subset of memory cells of a set of memory cells to be programmed. A first dynamic start voltage operation including a first set of programming pulses and a first set of program verify operations is executed on a first portion of the first subset of memory cells to identify a first dynamic start voltage level, the executing of the first dynamic start voltage operation includes causing the first set of programming pulses to be applied to at least a portion of the first group of wordlines. A second set of programming pulses including at least one programming pulse having the first dynamic start voltage level are caused to be applied to the first group of wordlines to program a second portion of the first subset of memory cells of the set of memory cells. A second group of wordlines associated with a second subset of memory cells to be programmed is identified. A second dynamic start voltage operation including a third set of programming pulses and a second set of program verify operations are executed on a first portion of the second subset of memory cells to identify a second dynamic start voltage level.

    MEMORY DEVICES FOR SUSPEND AND RESUME OPERATIONS
    83.
    发明申请
    MEMORY DEVICES FOR SUSPEND AND RESUME OPERATIONS 有权

    公开(公告)号：US20220208273A1

    公开(公告)日：2022-06-30

    申请号：US17382619

    申请日：2021-07-22

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Umberto Siciliani ,  Floriano Montemurro ,  Eric N. Lee ,  Dheeraj Srinivasan

    IPC: G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  G11C7/10

    Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation; and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.

    MEMORY DEVICES FOR MULTILPLE READ OPERATIONS
    84.
    发明申请
    MEMORY DEVICES FOR MULTILPLE READ OPERATIONS 有权

    公开(公告)号：US20220189517A1

    公开(公告)日：2022-06-16

    申请号：US17463789

    申请日：2021-09-01

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Eric N. Lee ,  Kishore Kumar Muchherla ,  Jeffrey S. McNeil ,  Jung-Sheng Hoei

    IPC: G11C7/10 ,  G11C7/14 ,  G11C7/22

    Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.

    Methods of forming semiconductor device structures
    86.
    发明授权
    Methods of forming semiconductor device structures 有权

    公开(公告)号：US10910395B2

    公开(公告)日：2021-02-02

    申请号：US16202999

    申请日：2018-11-28

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee

    IPC: H01L27/11575 ,  H01L23/528 ,  H01L27/11548 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/1157

    Abstract: A semiconductor device structure comprises stacked tiers each comprising at least one conductive structure and at least one insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and at least one opening extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. The at least one conductive structure of each of the stacked tiers extends continuously from at least one of the steps of the at least one staircase structure and around the at least one opening to form at least one continuous conductive path extending completely across each of the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described.

    MEMORY DEVICES WITH DISTRIBUTED BLOCK SELECT FOR A VERTICAL STRING DRIVER TILE ARCHITECTURE
    87.
    发明申请
    MEMORY DEVICES WITH DISTRIBUTED BLOCK SELECT FOR A VERTICAL STRING DRIVER TILE ARCHITECTURE 审中-公开

    公开(公告)号：US20200258575A1

    公开(公告)日：2020-08-13

    申请号：US16862380

    申请日：2020-04-29

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee

    IPC: G11C16/08 ,  G11C8/12 ,  G11C8/08 ,  G11C5/02 ,  G11C16/04

    Abstract: Memory device are disclosed. A memory device may include multiple pairs of tiles. At least some of the pairs of tiles may include a block select circuit. At least one portion of the block select circuit within a first pair of tiles of the multiple pairs of tiles is offset from at least one other portion of the block select circuit within a second pair of tiles of the multiple pairs of tiles. Also, at least one pair of tiles of the multiple pair of tiles may include an associated vertical string driver offset from each of a first tile and a second tile of an associated pair of tiles.

    APPARATUSES AND METHODS FOR A MEMORY DIE ARCHITECTURE INCLUDING AN INTERFACE MEMORY
    89.
    发明申请
    APPARATUSES AND METHODS FOR A MEMORY DIE ARCHITECTURE INCLUDING AN INTERFACE MEMORY 有权
    包含界面记忆的记忆体建筑的装置和方法

    公开(公告)号：US20160070504A1

    公开(公告)日：2016-03-10

    申请号：US14942701

    申请日：2015-11-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Dean K. Nobunaga ,  Ali Feiz Zarrin Ghalam ,  Xiaojiang Guo ,  Eric N. Lee

    IPC: G06F3/06 ,  G06F13/40 ,  G06F12/08

    CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0683 ,  G06F12/0802 ,  G06F12/0893 ,  G06F13/1684 ,  G06F13/4068 ,  G06F2212/1016 ,  G06F2212/3042 ,  G11C5/066 ,  G11C7/1048 ,  G11C8/12 ,  G11C11/00

    Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus, The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.

    Abstract translation: 本文公开了用于减小数据总线上的电容的装置和方法。 根据一个或多个所描述的实施例，装置可以包括耦合到内部数据总线和命令和地址总线的多个存储器，每个存储器被配置为在命令和地址总线上接收命令。 多个存储器中的一个可以耦合到外部数据总线。多个存储器中的一个存储器可以被配置为当命令包括程序命令时将程序数据提供给内部数据总线，并且多个存储器中的另一个是 目标存储器，并且可以被配置为当命令包括读取命令并且多个存储器中的另一个是读取命令的目标存储器时，向外部数据总线提供读取数据。

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