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公开(公告)号：US20180225056A1
公开(公告)日：2018-08-09
申请号：US15945316
申请日：2018-04-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Frankie F. Roohparvar , Luca De Santis , Tommaso Vali , Kenneth J. Eldredge
CPC classification number: G06F3/0634 , G06F3/0626 , G06F3/0632 , G06F3/0679 , G06F3/0688 , G06F11/1064 , G06F11/2263 , G11C11/005 , G11C15/046 , G11C16/0483
Abstract: Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.
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公开(公告)号：US10020058B2
公开(公告)日：2018-07-10
申请号：US15690359
申请日：2017-08-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Luca De Santis , Tommaso Vali , Kenneth J. Eldredge , Frankie F. Roohparvar
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/26 , G11C16/3418
Abstract: Methods for operating a memory, and memory configured to perform similar methods, include programming a first series string of memory cells of a first group of memory cells such that pairs of complementary memory cells have complementary states to provide a first minterm, the first minterm comprising a plurality of first variables wherein each variable is enabled responsive to a state of its respective memory cell, and programming a second series string of memory cells of a second group of memory cells such that pairs of complementary memory cells have complementary states to provide a second minterm, the second minterm comprising the first minterm that is enabled responsive to the state of its respective memory cell, the second minterm further comprising a plurality of second variables that are each enabled responsive to the state of their respective memory cell.
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公开(公告)号：US09773558B2
公开(公告)日：2017-09-26
申请号：US15132455
申请日：2016-04-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Luca De Santis , Tommaso Vali , Kenneth J. Eldredge , Frankie F. Roohparvar
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/26 , G11C16/3418
Abstract: Methods for operating memory cells include applying a respective minterm, comprising a plurality of variables, to control gates of series strings of memory cells, each series string programmed as a plurality of pairs of complementary memory cells such that certain ones of the plurality of variables are enabled, and logically combining each of the minterms into a logic function output. Memories include a plurality of memory cells configured in series strings of memory cells, wherein each series string of memory cells is configured to provide a minterm comprising a plurality of variables, each variable enabled responsive to a state of an associated, respective memory cell.
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公开(公告)号：US20160358661A1
公开(公告)日：2016-12-08
申请号：US15241496
申请日：2016-08-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tommaso Vali , Kenneth J. Eldredge , Frankie F. Roohparvar , Luca De Santis
CPC classification number: G11C16/26 , G06N3/04 , G06N3/0454 , G06N3/063 , G11C7/1006 , G11C7/106 , G11C16/0483 , G11C16/08
Abstract: Methods of operating memory include generating a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line. Methods of operating memory further include generating data values indicative of levels of a property sensed from data lines while applying potentials to control gates of memory cells of strings of series-connected memory cells connected to those data lines, performing a logical operation on a set of data values comprising those data values, and determining a potential to be applied to control gates of different memory cells of those strings of series-connected memory cells in response to an output of the logical operation on the set of data values.
Abstract translation: 操作存储器的方法包括产生指示从数据线感测的属性的电平的数据值，同时向连接到该数据线的多个串联连接的存储器单元串的存储器单元的控制栅极施加电位。 操作存储器的方法还包括产生指示从数据线感测的属性的电平的数据值，同时施加电位以控制连接到那些数据线的串联存储器单元的串的存储器单元的栅极，对一组 包括这些数据值的数据值，以及响应于对该组数据值的逻辑运算的输出，确定要应用于串联存储器单元串的不同存储单元的控制栅极的电位。
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公开(公告)号：US20160267953A1
公开(公告)日：2016-09-15
申请号：US15162128
申请日：2016-05-23
Applicant: Micron Technology, Inc.
Inventor： Mauro Castelli , Luca De Santis , Luigi Pilolli , Maria Luisa Gallese
Abstract: Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.
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Patent Agency Ranking
公开(公告)号：US20160064052A1
公开(公告)日：2016-03-03
申请号：US14476323
申请日：2014-09-03
Applicant: Micron Technology, Inc.
Inventor： Mauro Castelli , Luca De Santis , Luigi Pilolli , Maria Luisa Gallese
Abstract: Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.
Abstract translation: 一些实施例包括具有耦合到多个存储器设备，存储器单元和模块以对存储器单元执行操作的节点的装置和方法，以使得在节点处的信号的电平的水平依次改变至少一个 以请求执行操作的特定阶段，使得该请求可由存储器件检测，并且在请求被确认之后执行操作的特定阶段。 描述其他实施例。
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公开(公告)号：US20130227203A1
公开(公告)日：2013-08-29
申请号：US13846638
申请日：2013-03-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Giulio Marotta , Luca De Santis , Tommaso Vali
IPC: G06F12/02
CPC classification number: G11C16/16 , G06F12/0246 , G06F2212/7202 , G11C2211/5641
Abstract: Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode.
Abstract translation: 公开了装置和方法，例如基于特性在单级单元（SLC）和多级单元（MLC）之间的NAND闪速存储器中提供动态块分配的装置和方法。 在一个实施例中，存储器控制器基于可用于使用的存储器的量，在SLC模式和MLC模式之间的编程和/或重新编程块之间动态切换。 当内存使用量低时，使用SLC模式。 当内存使用率高时，使用MLC模式。 动态块分配允许内存控制器获得SLC模式的性能和可靠性优势，同时保持MLC模式的节省空间的优势。
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公开(公告)号：US11568940B2
公开(公告)日：2023-01-31
申请号：US17408774
申请日：2021-08-23
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tommaso Vali , Luca De Santis , Ramin Ghodsi
Abstract: Memory having a controller configured to cause the memory to determine a respective raw data value of a plurality of possible raw data values for each memory cell of a plurality of memory cells, count occurrences of each raw data value for a first set of memory cells of the plurality of memory cells, store a cumulative number of occurrences for each raw data value, determine a plurality of valleys of the stored cumulative number of occurrences for each raw data value with each valley corresponding to a respective raw data value of the plurality of possible raw data values, and, for each memory cell of a second set of memory cells of the plurality of memory cells, determine a data value for that memory cell in response to the raw data value for that memory cell and the respective raw data values of the plurality of valleys.
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公开(公告)号：US11437103B2
公开(公告)日：2022-09-06
申请号：US17111721
申请日：2020-12-04
Applicant: Micron Technology, Inc.
Inventor： Umberto Minucci , Tommaso Vali , Fernanda Irrera , Luca De Santis
Abstract: A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so that current flows through the first and second memory cells, and generating an output responsive to the current. The first voltage and a threshold voltage of the second memory cell can be such that the current is proportional to a product of the first voltage and the threshold voltage of the second memory cell.
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公开(公告)号：US20220011970A1
公开(公告)日：2022-01-13
申请号：US16946871
申请日：2020-07-09
Applicant: Micron Technology, Inc.
Inventor： Luca Nubile , Luca De Santis
IPC: G06F3/06
Abstract: A processing device in a memory sub-system assigns each of a plurality of memory units associated with one or more memory die of a memory device a unique address by which each of the plurality of memory units is identified. The processing device further sends a multi-unit status command to the memory device, the multi-unit status command specifying a subset of the plurality of memory units using corresponding unique addresses and receives a response to the multi-unit status command, the response comprising a multi-bit value comprising a plurality of bits, wherein each bit of the plurality of bits represents a status of one or more parameters of a plurality of parameters for a corresponding one of the plurality of memory units.
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