公开(公告)号：US20100120950A1

公开(公告)日：2010-05-13

申请号：US12522835

申请日：2008-01-11

申请人： Takeaki Saiki ,  Makoto Iwai ,  Anil Kumar Tomar

发明人： Takeaki Saiki ,  Makoto Iwai ,  Anil Kumar Tomar

IPC分类号： C08K5/34 ,  C07F7/02

CPC分类号： C07F7/188 ,  C07F7/1804

摘要： A method for manufacturing a bis(silatranylalkyl) polysulfide by heating a bis(trialkoxysilylalkyl) polysulfide and triethanolamine in the presence of a catalytic quantity of an alkali-metal alcoholate, thus substituting all Si-bonded alkoxy groups of the bis(trialkoxysilylalkyl) polysulfide with a (OCH2CH2)3N group; a method for the preparation of a mixture of a bis(silatranylalkyl) polysulfide and a (silatranyalkyl) (trialkoxysilyl) disulfide or a mixture of a bis(silatranylalkyl) polysulfide, a (silatranylalkyl) (trialkoxysilyl) disulfide, and a bis(trialkoxysilylalkyl) polysulfide by heating a bis(trialkoxysilylalkyl) polysulfide and triethanolamine in the presence of a catalytic quantity of an alkali-metal alcoholate, thus substituting a part of Si-bonded alkoxy groups of the bis(trialkoxysilylalkyl) polysulfide with a (OCH2CH2)3N group; a mixture of a bis(silatranylalkyl) polysulfide and a (silatranylalkyl)(trialkoxysilyl) disulfide; a mixture of a bis(silatranylalkyl) polysulfide, a (silatranylalkyl)(trialkoxysilyl) disulfide, and a bis(trialkoxysilylalkyl) polysulfide; and a rubber composition containing the aforementioned mixture.

摘要翻译： 在催化量的碱金属醇化物的存在下加热双（三烷氧基甲硅烷基）多硫化物和三乙醇胺，从而将双（三烷氧基甲硅烷基烷基）多硫化物的所有Si键合的烷氧基与 （OCH 2 CH 2）3 N基团; 制备双（硅烷基烷基烷基）多硫化物和（硅烷基烷基）（三烷氧基甲硅烷基）二硫化物的混合物或双（硅烷基烷基烷基）多硫化物，（硅烷基烷基）（三烷氧基甲硅烷基）二硫化物和双（三烷氧基甲硅烷基） 通过在催化量的碱金属醇化物的存在下加热双（三烷氧基甲硅烷基）多硫化物和三乙醇胺，从而用（OCH 2 CH 2）3 N基取代双（三烷氧基甲硅烷基烷基）多硫化物的一部分Si键合的烷氧基， 双（甲硅烷基烷基）多硫化物和（硅烷基烷基烷基）（三烷氧基甲硅烷基）二硫化物的混合物; （硅烷基烷基）多硫化物，（硅烷基烷基）（三烷氧基甲硅烷基）二硫化物和双（三烷氧基甲硅烷基烷基）多硫化物的混合物; 和含有上述混合物的橡胶组合物。

公开(公告)号：US07616502B2

公开(公告)日：2009-11-10

申请号：US12108111

申请日：2008-04-23

申请人： Makoto Iwai

发明人： Makoto Iwai

IPC分类号： G11C11/34

CPC分类号： G11C16/12

摘要： A semiconductor memory device comprising: a memory cell array having memory cell units each formed by connecting a plurality of memory cells; a first and a second select gate transistors, the first select gate transistor being connected between one end of the memory cell array and a common source line, the second select gate transistor being connected between the other end of the memory cell array and bit lines; word lines acting also as control gates of the memory cells; a first select gate voltage-generating circuit for generating a first select gate voltage; a second select gate-setting circuit for setting an instructed value of a second select gate voltage; a second select gate voltage-generating circuit for generating the second select gate voltage based on the set, instructed value; a first transfer circuit for transferring the first select gate voltage generated by the first select gate voltage-generating circuit to a second select gate; a discharging circuit for discharging the first select gate voltage transferred to the second select gate; and a discharging characteristics selection circuit for selecting discharging characteristics of the discharging circuit.

摘要翻译： 一种半导体存储器件，包括：存储单元阵列，具有通过连接多个存储单元形成的存储单元单元; 第一和第二选择栅极晶体管，第一选择栅晶体管连接在存储单元阵列的一端和公共源极线之间，第二选择栅极晶体管连接在存储单元阵列的另一端和位线之间; 字线也用作存储器单元的控制栅极; 用于产生第一选择栅极电压的第一选择栅极电压产生电路; 第二选择栅极设定电路，用于设定第二选择栅极电压的指示值; 第二选择栅极电压产生电路，用于基于所设定的指示值产生第二选择栅极电压; 用于将由第一选择栅极电压产生电路产生的第一选择栅极电压转移到第二选择栅极的第一转移电路; 放电电路，用于对传送到第二选择栅极的第一选择栅极电压进行放电; 以及用于选择放电电路的放电特性的放电特性选择电路。

公开(公告)号：US07529131B2

公开(公告)日：2009-05-05

申请号：US11558714

申请日：2006-11-10

申请人： Makoto Iwai ,  Yoshihisa Watanabe

发明人： Makoto Iwai ,  Yoshihisa Watanabe

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26

摘要： A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.

摘要翻译： 非易失性半导体存储器包括：存储单元单元，包括具有电荷累积层和控制电极的多个存储单元，所述存储单元串联电连接; 多个字线，其各自电连接到所述多个存储单元的所述控制电极; 在所述存储单元单元的一端电连接到所述存储单元的源极线; 在所述存储单元单元的另一端电连接到所述存储单元的位线; 以及控制信号生成电路，其在数据读出操作期间，从连接到未选择的存储器的未选择的字线的选择时刻开始，选择连接到所述存储单元的所述存储单元的字线的定时。

公开(公告)号：US20080266967A1

公开(公告)日：2008-10-30

申请号：US12108111

申请日：2008-04-23

申请人： Makoto Iwai

发明人： Makoto Iwai

IPC分类号： G11C16/06

CPC分类号： G11C16/12

摘要： A semiconductor memory device comprising: a memory cell array having memory cell units each formed by connecting a plurality of memory cells; a first and a second select gate transistors, the first select gate transistor being connected between one end of the memory cell array and a common source line, the second select gate transistor being connected between the other end of the memory cell array and bit lines; word lines acting also as control gates of the memory cells; a first select gate voltage-generating circuit for generating a first select gate voltage; a second select gate-setting circuit for setting an instructed value of a second select gate voltage; a second select gate voltage-generating circuit for generating the second select gate voltage based on the set, instructed value; a first transfer circuit for transferring the first select gate voltage generated by the first select gate voltage-generating circuit to a second select gate; a discharging circuit for discharging the first select gate voltage transferred to the second select gate; and a discharging characteristics selection circuit for selecting discharging characteristics of the discharging circuit.

摘要翻译： 一种半导体存储器件，包括：存储单元阵列，具有通过连接多个存储单元形成的存储单元单元; 第一和第二选择栅极晶体管，第一选择栅晶体管连接在存储单元阵列的一端和公共源极线之间，第二选择栅极晶体管连接在存储单元阵列的另一端和位线之间; 字线也用作存储器单元的控制栅极; 用于产生第一选择栅极电压的第一选择栅极电压产生电路; 第二选择栅极设定电路，用于设定第二选择栅极电压的指示值; 第二选择栅极电压产生电路，用于基于所设定的指示值产生第二选择栅极电压; 用于将由第一选择栅极电压产生电路产生的第一选择栅极电压转移到第二选择栅极的第一转移电路; 放电电路，用于对传送到第二选择栅极的第一选择栅极电压进行放电; 以及用于选择放电电路的放电特性的放电特性选择电路。

公开(公告)号：US20080049509A1

公开(公告)日：2008-02-28

申请号：US11844096

申请日：2007-08-23

申请人： Makoto Iwai

发明人： Makoto Iwai

IPC分类号： G11C16/00

CPC分类号： G11C16/26

摘要： A nonvolatile semiconductor memory device includes a memory cell array 101 having a plurality memory strings, each of said plurality of memory strings having a plurality of memory cells connected in series, each of said plurality of memory cells having a control gate, said plurality of memory cells including a read-memory cell whose programmed data is read and a plurality of non-read-memory cells other than said read-memory cell, each said control gate of each said plurality of non-read-memory cells being applied with a read pass voltage to read said programmed data programmed in said read-memory cell, a read pass voltage application control part 201 for applying a predetermined read pass voltage to the control gates of all non-read memory cells among said plurality of memory cells other than a read-memory cell whose stored data are read, and a clock signal cycle control part 203 for controlling a cycle of a clock signal which is provided to said read pass voltage application control part 201.

摘要翻译： 非易失性半导体存储器件包括具有多个存储器串的存储单元阵列101，所述多个存储器串中的每一个具有串联连接的多个存储单元，所述多个存储单元中的每一个具有控制栅极，所述多个存储器 包括读取其编程数据的读取存储器单元和除所述读取存储单元之外的多个非读取存储单元的单元，每个所述多个非读取存储单元的所述控制栅极被应用于读取 读取所述读取存储单元中编程的所述编程数据的读出通过电压施加控制部201，用于将预定的读取通过电压施加到所述多个存储单元中除了 其存储的数据被读取的读出存储单元和用于控制提供给所述读取通过电压施加控制p的时钟信号的周期的时钟信号周期控制部分203 艺术201。

公开(公告)号：US20060287546A1

公开(公告)日：2006-12-21

申请号：US10551528

申请日：2004-03-30

申请人： Makoto Iwai ,  Mitsuyoshi Hamada

发明人： Makoto Iwai ,  Mitsuyoshi Hamada

IPC分类号： C07F7/10

CPC分类号： C07F7/1804

摘要： A new nitrogen-containing organosilicon compound contains tertiary amine groups and carbonyl groups wherein the tertiary amine groups are selected from R1R2N—(where R1 and R2 are the same or different univalent hydrocarbon groups of 1-15 carbon atoms), alicyclic amino groups, or heterocyclic amino groups containing in their rings one or more tertiary amine groups.

摘要翻译： 新的含氮有机硅化合物含有叔胺基团和羰基，其中叔胺基团选自R1R2N-（其中R1和R2是相同或不同的1-15个碳原子的一价烃基），脂环族氨基或 在其环中含有一个或多个叔胺基团的杂环氨基。

公开(公告)号：US08848446B2

公开(公告)日：2014-09-30

申请号：US13450008

申请日：2012-04-18

申请人： Makoto Iwai

发明人： Makoto Iwai

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3481

摘要： A nonvolatile semiconductor memory device includes bit lines, word lines, NAND strings, source lines, first and second select gate transistors, and a controller. After giving a first potential to the second select gate transistors, the controller gives a second potential lower than the first potential to the second select gate transistors, gives a third potential to the memory cells which are insufficient in the writing, gives a fourth potential higher than the third potential to the memory cells which are just before completion of the writing, and gives a fifth potential higher than the fourth potential to the memory cells which are completed in the writing. The first potential is capable of turning on the second select gate transistors. The second potential is capable of turning off the second select gate transistors.

摘要翻译： 非易失性半导体存储器件包括位线，字线，NAND串，源极线，第一和第二选择栅晶体管以及控制器。 在向第二选择栅极晶体管施加第一电位之后，控制器向第二选择栅晶体管提供低于第一电位的第二电位，向写入不足的存储单元给予第三电位，给予第四电位更高 比在写入完成之前的存储单元的第三个电位高，并且给写入中完成的存储单元赋予比第四个电位高的第五个电位。 第一电位能够接通第二选择栅极晶体管。 第二电位能够关断第二选择栅晶体管。

公开(公告)号：US08568532B2

公开(公告)日：2013-10-29

申请号：US13315871

申请日：2011-12-09

申请人： Makoto Iwai ,  Shuhei Higashihara ,  Yusuke Mori ,  Yasuo Kitaoka ,  Naoya Miyoshi

发明人： Makoto Iwai ,  Shuhei Higashihara ,  Yusuke Mori ,  Yasuo Kitaoka ,  Naoya Miyoshi

IPC分类号： C30B19/06

CPC分类号： C30B29/403 ,  C30B9/10 ,  C30B35/002

摘要： Materials of a nitride single crystal of a metal belonging to III group and a flux are contained in a crucible, which is contained in a reaction container, the reaction container is contained in an outer container, the outer container is contained in a pressure container, and nitrogen-containing atmosphere is supplied into the outer container and melt is generated in the crucible to grow a nitride single crystal of a metal belonging to III group. The reaction container includes a main body containing the crucible and a lid. The main body includes a side wall having a fitting face and a groove opening at the fitting face and a bottom wall. The lid has an upper plate part including a contact face for the fitting face of the main body and a flange part extending from the upper plate part and surrounding an outer side of said side wall.

摘要翻译： 属于III族的金属的氮化物单晶和助熔剂的材料包含在容纳在反应容器中的坩埚中，反应容器容纳在外容器中，外容器容纳在压力容器中， 向外容器供给含氮气氛，在坩埚中产生熔融物，生长属于III族的金属的氮化物单晶。 反应容器包括容纳坩埚和盖的主体。 主体包括具有配合面的侧壁和在配合面处的槽开口和底壁。 盖具有上板部，其包括用于主体的嵌合面的接触面和从上板部延伸并围绕所述侧壁的外侧的凸缘部。

公开(公告)号：US08501141B2

公开(公告)日：2013-08-06

申请号：US12662006

申请日：2010-03-26

申请人： Takayuki Sato ,  Seiji Nagai ,  Makoto Iwai ,  Shuhei Higashihara ,  Yusuke Mori ,  Yasuo Kitaoka

发明人： Takayuki Sato ,  Seiji Nagai ,  Makoto Iwai ,  Shuhei Higashihara ,  Yusuke Mori ,  Yasuo Kitaoka

IPC分类号： C01B21/06 ,  C30B15/00 ,  C30B9/00 ,  C30B19/00 ,  C30B11/00 ,  C30B25/00 ,  C30B28/14 ,  H01L21/00 ,  H01L33/00 ,  H01L21/02 ,  H01B1/02 ,  H01B1/04

CPC分类号： C30B9/12 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02625

摘要： An object of the present invention is to effectively add Ge in the production of GaN through the Na flux method. In a crucible, a seed crystal substrate is placed such that one end of the substrate remains on the support base, whereby the seed crystal substrate remains tilted with respect to the bottom surface of the crucible, and gallium solid and germanium solid are placed in the space between the seed crystal substrate and the bottom surface of the crucible. Then, sodium solid is placed on the seed crystal substrate. Through employment of this arrangement, when a GaN crystal is grown on the seed crystal substrate through the Na flux method, germanium is dissolved in molten gallium before formation of a sodium-germanium alloy. Thus, the GaN crystal can be effectively doped with Ge.

摘要翻译： 本发明的目的是通过Na通量法有效地添加Ge生产GaN。 在坩埚中，放置晶种衬底，使得衬底的一端保留在支撑基底上，由此籽晶衬底相对于坩埚的底表面保持倾斜，并且将镓固体和锗固体放置在 晶种基板与坩埚底面之间的空间。 然后，将钠固体置于晶种衬底上。 通过使用这种布置，当GaN晶体通过Na通量法在籽晶衬底上生长时，锗在形成钠 - 锗合金之前溶解在熔融镓中。 因此，GaN晶体可以有效地掺杂Ge。

公开(公告)号：US08477534B2

公开(公告)日：2013-07-02

申请号：US13490541

申请日：2012-06-07

申请人： Makoto Iwai ,  Hiroshi Nakamura

发明人： Makoto Iwai ,  Hiroshi Nakamura

IPC分类号： G11C16/04

CPC分类号： G11C16/3459 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3436 ,  G11C16/3454

摘要： A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

摘要翻译： 存储器包括第一和第二选择栅极晶体管，存储器单元，源极线，位线，连接到作为验证读取的目标的所选存储单元的选定字线，连接的未选择字线 到除所选存储单元之外的未选择的存储单元，用于产生提供给所选择的字线的所选择的读取电位并产生大于所选择的读取电位的未被选择的读取电位的电位产生电路， 以及控制电路，其通过验证被选择的存储器单元的单元电流属于两个值隔离的三个区域中的哪个区域属于三个组中的一个，将选择的存储单元的阈值电压分类为三个组中的一个 当所选择的读取电位为第一值时。