公开(公告)号：US6035365A

公开(公告)日：2000-03-07

申请号：US200446

申请日：1998-11-27

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G06F13/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: A synchronous memory device having at least one memory section which includes a plurality of memory cells. The memory device comprises a register to store a value which is representative of a delay time after which the memory device responds to a read request and clock receiver circuitry to receive first and second external clock signals. The memory device also includes an output driver(s) to output data on a bus, in response to a read request and in accordance with the delay time, wherein a first portion of the data is output synchronously with respect to the first external clock signal and a second portion of the data is output synchronously with respect to the second external clock signal. The memory device may include a delay locked loop to generate internal clock signal(s) using the external clock signal(s). The output drivers output data on the bus in response to the internal clock signal(s). The memory device may include input receiver circuitry, coupled to the bus, the receive the read request, wherein the read request is sampled from the bus synchronously with respect to the first external clock signal.

Abstract translation: 一种具有至少一个包括多个存储单元的存储器部分的同步存储器件。 该存储器件包括一个寄存器，用于存储表示延迟时间的值，在该延迟时间之后，存储器件响应于读取请求，并且时钟接收器电路接收第一和第二外部时钟信号。 存储器件还包括响应于读取请求并根据延迟时间在总线上输出数据的输出驱动器，其中数据的第一部分相对于第一外部时钟信号被同步输出 并且数据的第二部分相对于第二外部时钟信号被同步地输出。 存储器件可以包括使用外部时钟信号产生内部时钟信号的延迟锁定环路。 输出驱动器响应于内部时钟信号在总线上输出数据。 存储器件可以包括耦合到总线的输入接收器电路，接收读取请求，其中相对于第一外部时钟信号同步从总线对读取请求进行采样。

公开(公告)号：US5953263A

公开(公告)日：1999-09-14

申请号：US196200

申请日：1998-11-20

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F13/16 ,  G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1066 ,  G06F13/161 ,  G06F13/1689 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1069 ,  G11C2207/108 ,  Y02B60/1228

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Abstract translation: 本发明包括一个包括至少两个半导体器件的存储器子系统，包括连接到总线的至少一个存储器件，其中总线包括用于承载所有存储器件所需的所有地址，数据和控制信息的多条总线 ，其中控制信息包括设备选择信息，并且总线具有比单个地址中的位数少得多的总线，并且总线承载设备选择信息，而不需要直接连接到各个设备的单独的设备选择线 。 本发明还包括用于主设备和从设备在总线上通信的协议，以及用于每个设备中的寄存器以区分每个设备并允许总线请求被引导到单个或所有设备的协议。 本发明包括对现有技术设备的修改，以允许它们实现本发明的新特征。 在一个优选实施方式中，8个总线数据线和一个AddressValid总线携带地址，数据和控制信息，用于高达40位宽的存储器地址。

公开(公告)号：US5928343A

公开(公告)日：1999-07-27

申请号：US098387

申请日：1998-06-16

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G06F13/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: A method and apparatus for assigning identification values to memories. A master resets identifiers of a first memory and a second memory by sending a reset signal on a line that is coupled in a daisy-chained manner to the first and second memories and also coupled to the master. The master places a first identification value on a data bus coupled to the master and to the first and second memories. The first memory stores the first identification value on the data bus as an identifier for the first memory when the master sends a first storage signal to the first memory via the daisy-chained line. The master places a second identification value on the data bus. The second memory stores the second identification value on the data bus as an identifier for the second memory when the master sends a second storage signal to the second memory via the daisy-chained line.

Abstract translation: 一种用于将识别值分配给存储器的方法和装置。 主机通过以菊花链方式耦合到第一和第二存储器并且还耦合到主机的线路上发送复位信号来复位第一存储器和第二存储器的标识符。 主设备在耦合到主设备的数据总线和第一和第二存储器上放置第一标识值。 当主设备通过菊花链将第一存储信号发送到第一存储器时，第一存储器将数据总线上的第一标识值存储为第一存储器的标识符。 主机在数据总线上放置第二个标识值。 第二存储器，当主机通过菊花链发送第二存储信号到第二存储器时，将第二识别值存储在数据总线上作为第二存储器的标识符。

公开(公告)号：US5606717A

公开(公告)日：1997-02-25

申请号：US847651

申请日：1992-03-05

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G06F13/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: An interfacing circuitry for a semiconductor circuit of a computer system selects the semiconductor circuit for a device operation in accordance with data, addresses, and control information received from a multiline bus of the computer system in a form of packets. The computer system has a plurality of semiconductor circuits. The interfacing circuitry is coupled to the multiline bus. The multiline bus has a total number of lines less than a total number of bits in any single address. The interfacing circuitry resides inside the semiconductor circuit and includes a decoder for decoding the packets received to identify the data, addresses, and control information. A control logic circuitry is coupled to the decoder circuitry for controlling device operation of the first semiconductor circuit in accordance with the data, addresses, and control information received. A register circuitry is coupled to the decoder and the control logic circuitry for storing a first value corresponding to a first predetermined time period during which the interfacing circuitry must wait before transmitting reply information through the multiline bus in response to the data, addresses, and control information received. The register circuitry applies the first value to the control logic circuitry to cause the control logic circuitry to wait for the first predetermined time period before accessing the multiline bus for transmitting the reply information.

Abstract translation: 用于计算机系统的半导体电路的接口电路根据从计算机系统的多行总线以分组的形式接收的数据，地址和控制信息来选择用于设备操作的半导体电路。 计算机系统具有多个半导体电路。 接口电路耦合到多线总线。 多行总线的总线数小于任何单个地址中的总位数。 接口电路位于半导体电路内，并且包括用于对接收到的分组进行解码以识别数据，地址和控制信息的解码器。 控制逻辑电路耦合到解码器电路，用于根据所接收的数据，地址和控制信息来控制第一半导体电路的设备操作。 寄存器电路耦合到解码器和控制逻辑电路，用于存储对应于第一预定时间段的第一值，在该第一预定时间段期间，接口电路必须在响应于数据，地址和控制在通过多线总线发送应答信息之前等待 收到的资料 寄存器电路将第一值应用于控制逻辑电路，以使得控制逻辑电路在访问多行总线之前等待第一预定时间段以发送回复信息。

公开(公告)号：US5243703A

公开(公告)日：1993-09-07

申请号：US849211

申请日：1992-03-05

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F11/00 ,  G06F11/10 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C7/1066 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/006 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108

Abstract: An apparatus for synchronously generating a first clock signal in a first circuitry and a second clock signal in a second circuitry of a data processing system is described. A clock generating circuitry generates a global clock signal. A transmission line transfers the global clock signal from its first end to its second end and includes a midpoint between the first end and the second end. A first clock signal generation circuit is coupled at a first point between the first end and the midpoint and a second point between the midpoint and the second end. The first and second points have the same line length to the midpoint. The first clock signal generation circuit generates the first clock signal at a first timing point which is halfway between the global clock signal with a first propagation delay from the first end to the first point and the signal with a second propagation delay from the first end to the second point. A second clock signal generation circuit is coupled at a third point between the first end and the midpoint and a fourth point between the midpoint and the second end. The third and fourth points have the same line length to the midpoint. The second clock signal generation circuit generates the second clock signal at a second timing point which is halfway between the global clock signal with a third propagation delay from the first end to the third point and the signal with a fourth propagation delay from the first end to the fourth point. The first timing point is the same as the second timing point such that the first signal is synchronized with the second signal.

Abstract translation: 描述了一种在数据处理系统的第二电路中同步产生第一电路中的第一时钟信号和第二时钟信号的装置。 时钟发生电路产生全局时钟信号。 传输线将全局时钟信号从其第一端传送到其第二端，并且包括第一端和第二端之间的中点。 第一时钟信号产生电路在第一端和中点之间的第一点处耦合，并且在中点和第二端之间连接第二点。 第一点和第二点与中点具有相同的线长度。 第一时钟信号产生电路在第一定时点处产生第一时钟信号，该第一定时点位于全局时钟信号之间的第一时钟信号与从第一端到第一点的第一传播延迟，以及从第一端到第二传播延迟的信号 第二点。 第二时钟信号产生电路在第一端和中点之间的第三点耦合，并且在中点和第二端之间连接第四点。 第三点和第四点与中点具有相同的行长度。 第二时钟信号产生电路在第二定时点产生第二时钟信号，该第二定时点位于具有从第一端到第三点的第三传播延迟的全局时钟信号之间的中间，以及从第一端到第四传播延迟的信号 第四点。 第一定时点与第二定时点相同，使得第一信号与第二信号同步。

公开(公告)号：US08185853B2

公开(公告)日：2012-05-22

申请号：US12594873

申请日：2008-02-28

Applicant: Jaeha Kim ,  Kevin D. Jones ,  Mark Horowitz

Inventor： Jaeha Kim ,  Kevin D. Jones ,  Mark Horowitz

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: Embodiments in the present disclosure pertain to domain translators. A domain translator converts a variable from one domain to a different domain. Domains include, but are not limited to, voltage, current, frequency, phase, delay, and duty-cycle. In particular, domain translators enable conversion between standard voltage and current domains commonly used by circuit simulators to other domains such as frequency, phase, delay, duty-cycle, etc., so that linear analysis can be performed on a wide range of circuits that exhibit linear behavior in domains other than voltage and current.

Abstract translation: 本公开的实施例涉及域翻译器。 域转换器将变量从一个域转换为不同的域。 域包括但不限于电压，电流，频率，相位，延迟和占空比。 特别地，域转换器使得电路模拟器通常使用的标准电压和电流域之间能够转换到诸如频率，相位，延迟，占空比等其他领域，使得可以在宽范围的电路上执行线性分析， 在电压和电流以外的领域表现出线性行为。

公开(公告)号：US08116366B2

公开(公告)日：2012-02-14

申请号：US12149157

申请日：2008-04-28

Applicant: Toshitsugu Kawashima ,  Mark Horowitz

Inventor： Toshitsugu Kawashima ,  Mark Horowitz

IPC: H03H7/30 ,  H03K5/159

CPC classification number: H04L25/03057 ,  H04L25/03235

Abstract: Disclosed is a delayed decision feedback sequence estimator comprising a delayed decision feedback sequence estimator main unit including DDFSE computing unit group including (L+M) DDFSE computing units, equal in number to a length of each of plurality of blocks into which a received data symbol sequence is divided; wherein (L+M) DDFSE computing units are connected in a pipeline configuration to execute delayed decision feedback sequence estimation of the blocks in parallel; and an edge effect detection and correction circuit that detects an edge effect due to processing the delayed decision feedback sequence estimation of the separated block and corrects a relevant bit error.

Abstract translation: 公开了一种延迟判定反馈序列估计器，其包括延迟判定反馈序列估计器主单元，该延迟判定反馈序列估计器主单元包括DDFSE计算单元组，其包括（L + M）DDFSE计算单元，其数量等于多个块中的每一个的长度，其中接收的数据符号 序列分为 其中（L + M）DDFSE计算单元以流水线配置连接以并行地执行块的延迟判定反馈序列估计; 以及边缘效应检测和校正电路，其检测由于处理分离块的延迟的判定反馈序列估计的边缘效应并校正相关的位错误。

公开(公告)号：US08027531B2

公开(公告)日：2011-09-27

申请号：US11187699

申请日：2005-07-21

Applicant: Bennett Wilburn ,  Neel Joshi ,  Marc C. Levoy ,  Mark Horowitz

Inventor： Bennett Wilburn ,  Neel Joshi ,  Marc C. Levoy ,  Mark Horowitz

IPC: G06K9/00 ,  G06K7/00 ,  G06T15/00 ,  H04N13/02 ,  H04N13/04

CPC classification number: H04N5/247 ,  H04N5/3532 ,  H04N5/357

Abstract: This invention relates to an apparatus and a method for video capture of a three-dimensional region of interest in a scene using an array of video cameras. The video cameras of the array are positioned for viewing the three-dimensional region of interest in the scene from their respective viewpoints. A triggering mechanism is provided for staggering the capture of a set of frames by the video cameras of the array. The apparatus has a processing unit for combining and operating on the set of frames captured by the array of cameras to generate a new visual output, such as high-speed video or spatio-temporal structure and motion models, that has a synthetic viewpoint of the three-dimensional region of interest. The processing involves spatio-temporal interpolation for determining the synthetic viewpoint space-time trajectory. In some embodiments, the apparatus computes a multibaseline spatio-temporal optical flow.

Abstract translation: 本发明涉及使用摄像机阵列在场景中对三维感兴趣区域进行视频采集的装置和方法。 阵列的摄像机被定位成从它们各自的视点观看场景中的感兴趣的三维区域。 提供了一种触发机制，用于通过阵列的摄像机交错捕获一组帧。 该装置具有处理单元，用于组合并操作由相机阵列捕获的一组帧，以产生新的视觉输出，例如高速视频或时空结构和运动模型，其具有合成视点 感兴趣的三维区域。 该处理涉及用于确定合成视点时空轨迹的时空插值。 在一些实施例中，该装置计算多基线时空光流。

公开(公告)号：US07859436B2

公开(公告)日：2010-12-28

申请号：US12258285

申请日：2008-10-24

Applicant: Carl Werner ,  Mark Horowitz ,  Pak Chau ,  Scott Best ,  Stefanos Sidiropoulos

Inventor： Carl Werner ,  Mark Horowitz ,  Pak Chau ,  Scott Best ,  Stefanos Sidiropoulos

IPC: H03M7/00

CPC classification number: H04L25/4917 ,  G06F13/1678 ,  G06F13/4068 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C8/10 ,  G11C11/56 ,  G11C27/02 ,  G11C2207/108 ,  H04L7/0331 ,  H04L7/0332 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0296 ,  H04L25/0298 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/08 ,  H04L25/4902

Abstract: A memory device includes a receiver to receive a first input data signal and to create an output signal corresponding to the first input data signal and a voltage representative of a second signal received earlier in time than the first input data signal. A memory system includes a memory controller and one or more memory devices, at least one or which includes a receiver to receive a first input data signal and to create an output signal corresponding to the first input data signal and a voltage representative of a second signal received earlier in time than the first input data signal.

Abstract translation: 存储器件包括接收器，用于接收第一输入数据信号并产生对应于第一输入数据信号的输出信号和代表在时间上比第一输入数据信号更早接收的第二信号的电压。 存储器系统包括存储器控制器和一个或多个存储器设备，至少一个存储器设备或包括接收器以接收第一输入数据信号并产生对应于第一输入数据信号的输出信号和表示第二信号的电压 比第一输入数据信号更早地接收。

公开(公告)号：US20100199237A1

公开(公告)日：2010-08-05

申请号：US12594873

申请日：2008-02-28

Applicant: Jaeha Kim ,  Kevin D. Jones ,  Mark Horowitz

Inventor： Jaeha Kim ,  Kevin D. Jones ,  Mark Horowitz

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: Embodiments in the present disclosure pertain to domain translators. A domain translator converts a variable from one domain to a different domain. Domains include, but are not limited to, voltage, current, frequency, phase, delay, and duty-cycle. In particular, domain translators enable conversion between standard voltage and current domains commonly used by circuit simulators to other domains such as frequency, phase, delay, duty-cycle, etc., so that linear analysis can be performed on a wide range of circuits that exhibit linear behavior in domains other than voltage and current.

Abstract translation: 本公开的实施例涉及域翻译器。 域转换器将变量从一个域转换为不同的域。 域包括但不限于电压，电流，频率，相位，延迟和占空比。 特别地，域转换器使得电路模拟器通常使用的标准电压和电流域之间能够转换到诸如频率，相位，延迟，占空比等其他领域，使得可以在宽范围的电路上执行线性分析， 在电压和电流以外的领域表现出线性行为。