公开(公告)号：US20050124127A1

公开(公告)日：2005-06-09

申请号：US10726500

申请日：2003-12-04

申请人： Tzu-En Ho ,  Chang-Rong Wu ,  Yi-Nan Chen ,  Kuo-Chien Wu

发明人： Tzu-En Ho ,  Chang-Rong Wu ,  Yi-Nan Chen ,  Kuo-Chien Wu

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

摘要： The present invention provides a method for manufacturing a stacked gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a metal layer, a barrier layer, and a tungsten layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.

摘要翻译： 本发明提供一种在半导体器件中制造堆叠栅极结构的方法。 该方法包括以下步骤：在半导体衬底上依次形成栅极电介质层，多晶硅层，金属层，势垒层和钨层，在氮气环境中进行快速热退火（RTA） 在所述钨层上形成氮化硅层，并将所述多层薄膜结构图案化为规定的形态。

公开(公告)号：US20050106887A1

公开(公告)日：2005-05-19

申请号：US10783467

申请日：2004-02-20

申请人： Yi-Nan Chen ,  Tse-Yao Huang ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Tse-Yao Huang ,  Hui-Min Mao

IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L21/302 ,  H01L21/461 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76897

摘要： A method of forming contact holes. A substrate on which a plurality of gate structures is formed is provided, wherein the gate structure comprises a gate, a gate capping layer, and a gate spacer. An insulating layer is formed on the gate structures and fills between the gate structures. The insulating layer is etched using the gate capping layers, the gate spacers, and the substrate as stop layers to form first contact holes between the gate structures to expose the substrate and the gate spacers and form second contact holes overlying each gate structure to expose the gate capping layers. A protective spacer is formed over each sidewall of the first contact holes and the second contact holes. The gate capping layer under each gate contact hole is etched using the protective spacer as a stop layer to expose the gate. The protective spacers are removed.

摘要翻译： 一种形成接触孔的方法。 提供形成有多个栅极结构的基板，其中栅极结构包括栅极，栅极覆盖层和栅极间隔物。 在栅极结构上形成绝缘层，并填充在栅极结构之间。 使用栅极覆盖层，栅极间隔物和衬底作为停止层来蚀刻绝缘层，以在栅极结构之间形成第一接触孔，以暴露衬底和栅极间隔物，并形成覆盖每个栅极结构的第二接触孔，以暴露出 门盖层。 在第一接触孔和第二接触孔的每个侧壁上形成保护隔离物。 在每个栅极接触孔下方的栅极覆盖层使用保护隔板作为停止层进行蚀刻，以露出栅极。 去除保护性间隔物。

公开(公告)号：US20050104063A1

公开(公告)日：2005-05-19

申请号：US10714952

申请日：2003-11-18

申请人： Ping Hsu ,  Yi-Nan Chen

发明人： Ping Hsu ,  Yi-Nan Chen

IPC分类号： G01R31/28 ,  G11C29/00 ,  H01L21/762 ,  H01L23/544 ,  H01L21/66 ,  G01R31/26 ,  H01L23/58 ,  H01L29/10

CPC分类号： H01L22/34 ,  G01R31/2884 ,  G11C29/006 ,  H01L21/76224

摘要： Disclosed is a. method for detecting STI void of a semiconductor wafer. The method of the present invention comprises steps of assigning a detecting area in a predetermined region of the wafer; forming active areas and gate strips crossing the active areas by the process synchronized with that for other regions of the wafer. Dielectric material is filled between the active areas. The adjacent portion between the active areas reaches a predetermined length at least. The electrical value of the gate strips is measured to determine whether there is any void in the dielectric filled between the active areas, thereby to derive whether there is any void generated in the STI between the active areas of the other regions of the wafer.

公开(公告)号：US20050101124A1

公开(公告)日：2005-05-12

申请号：US10702493

申请日：2003-11-07

申请人： Chang-Ming Wu ,  Shing-Yih Shih ,  Yi-Nan Chen

发明人： Chang-Ming Wu ,  Shing-Yih Shih ,  Yi-Nan Chen

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/76834

摘要： A via contact forming method. The method includes the steps of providing a substrate; forming a first dielectric layer on the substrate; forming a bit line in the first dielectric layer; forming a liner layer on the first dielectric layer containing the bit line; forming a second dielectric layer on the liner layer; in the second dielectric layer, forming a contact hole leading to the bit line; and filling the contact hole with metal to form a via contact. The via contact forming method in accordance with the present invention has high tolerance to misalignment between the via contact and the bit line, while maintaining low resistance and good electric performance.

摘要翻译： 通孔接触形成方法。 该方法包括提供基板的步骤; 在所述基板上形成第一电介质层; 在第一介电层中形成位线; 在包含所述位线的所述第一介质层上形成衬垫层; 在所述衬垫层上形成第二电介质层; 在第二电介质层中形成通向位线的接触孔; 并用金属填充接触孔以形成通孔接触。 根据本发明的通孔接触形成方法在保持低电阻和良好的电性能的同时对通孔接触和位线之间的未对准具有高容限性。

公开(公告)号：US06881670B2

公开(公告)日：2005-04-19

申请号：US10709264

申请日：2004-04-26

申请人： Tien-Sung Chen ,  Yi-Nan Chen ,  Jin-Tau Huang

发明人： Tien-Sung Chen ,  Yi-Nan Chen ,  Jin-Tau Huang

IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8222

CPC分类号： H01L21/76843 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76855 ,  H01L21/76867 ,  H01L21/7688

摘要： A process for fabricating interconnects is provided. First, a substrate having a dielectric layer and silicon-containing mask layer on the dielectric layer is provided. The dielectric layer is patterned to form an opening. Thereafter, a metallic glue layer is formed over the silicon-containing mask layer and the interior surfaces of the opening. A metallic layer is formed over the substrate to fill the opening and cover the metallic glue layer. A thermal treatment process is next carried out so that the metallic glue layer reacts with the silicon-containing mask layer to form a metal silicide layer. A portion of the metallic layer is removed to expose the metal silicide layer. A solution mixture containing hydrogen peroxide, sulfuric acid, water and hydrofluoric acid is used to remove the metal silicide layer. The silicon-containing mask layer is also removed to expose the dielectric layer. The solution mixture containing hydrogen peroxide, sulfuric acid, water and hydrofluoric acid can remove the metal silicide layer completely without damaging the metallic layer.

摘要翻译： 提供了制造互连的工艺。 首先，提供在电介质层上具有电介质层和含硅掩模层的基板。 将介电层图案化以形成开口。 此后，在含硅掩模层和开口的内表面上形成金属胶层。 金属层形成在衬底上以填充开口并覆盖金属胶层。 接下来进行热处理工艺，使得金属胶层与含硅掩模层反应形成金属硅化物层。 去除金属层的一部分以露出金属硅化物层。 使用含有过氧化氢，硫酸，水和氢氟酸的溶液混合物去除金属硅化物层。 还除去含硅掩模层以暴露介电层。 含有过氧化氢，硫酸，水和氢氟酸的溶液混合物可以完全去除金属硅化物层而不会损坏金属层。

公开(公告)号：US20050048761A1

公开(公告)日：2005-03-03

申请号：US10646896

申请日：2003-08-25

申请人： Chih-Ching Lin ,  Yi-Nan Chen

发明人： Chih-Ching Lin ,  Yi-Nan Chen

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/7685 ,  H01L21/76802 ,  H01L21/76865

摘要： Disclosed is a method for forming conducting wire and contact opening in a semiconductor device. The method comprises steps of providing a substrate; forming a first dielectric layer on the substrate; digging a via in the first dielectric layer and filling metal therein; forming a conductor layer on the first dielectric including the via; forming a metal layer on the conductor layer; removing unnecessary portions of the conductor/metal layers to define recesses, with the left portions to form conducting wires; applying a second dielectric layer to fill the recesses and performing planarization thereto to expose the conducting wires; forming a third dielectric layer; forming photoresist of predetermined pattern on the third dielectric layer; removing predetermined portion of the third dielectric layer to form a contact opening; and removing the photoresist.

摘要翻译： 公开了一种在半导体器件中形成导线和接触开口的方法。 该方法包括提供衬底的步骤; 在所述基板上形成第一电介质层; 在第一电介质层中挖掘通孔并在其中填充金属; 在包括通孔的第一电介质上形成导体层; 在导体层上形成金属层; 去除导体/金属层的不需要的部分以限定凹部，其中左部分形成导线; 施加第二电介质层以填充凹部并对其进行平坦化以暴露导线; 形成第三电介质层; 在所述第三介电层上形成预定图案的光致抗蚀剂; 去除所述第三电介质层的预定部分以形成接触开口; 并去除光致抗蚀剂。

公开(公告)号：US20050037622A1

公开(公告)日：2005-02-17

申请号：US10605238

申请日：2003-09-17

申请人： Min-Yi Hsu ,  Hsin-Jung Ho ,  Kun-Shin Huang ,  Yi-Nan Chen ,  Kaanlu Tzou

发明人： Min-Yi Hsu ,  Hsin-Jung Ho ,  Kun-Shin Huang ,  Yi-Nan Chen ,  Kaanlu Tzou

IPC分类号： H01L21/302 ,  H01L21/3213

CPC分类号： H01L21/02079 ,  H01L21/32134 ,  H01L21/32135

摘要： A method of reworking an integrated circuit device is described. A substrate having a dielectric layer, a barrier layer, a conductive layer and an anti-reflective layer formed thereon, is provided. The method of reworking the barrier layer, the conductive layer and the anti-reflective layer comprises removing the anti-reflection layer by performing a dry etching process, removing the conductive layer by performing a wet etching process, and then removing the barrier layer by performing a chemical machine polishing process.

摘要翻译： 描述了对集成电路器件进行返工的方法。 提供了具有形成在其上的电介质层，阻挡层，导电层和抗反射层的基板。 对阻挡层，导电层和抗反射层进行再加工的方法包括通过进行干蚀刻工艺去除抗反射层，通过进行湿蚀刻工艺去除导电层，然后通过执行 化学机械抛光工艺。

公开(公告)号：US06808979B1

公开(公告)日：2004-10-26

申请号：US10640097

申请日：2003-08-13

申请人： Shian-Jyh Lin ,  Yi-Nan Chen

发明人： Shian-Jyh Lin ,  Yi-Nan Chen

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L29/66181

摘要： A method for forming a vertical transistor and a trench capacitor. A semiconductor substrate having a pad stacked layer on the surface and a trench formed therein is provided. A capacitor is formed at the bottom part of the trench and a portion of the upper sidewall of the trench is exposed. A conductive wire is then formed on the capacitor, followed by forming a dielectric layer on the exposed sidewalls of the trench. A trench top dielectric is then formed by liquid phase deposition on the conductive wire. A transistor is then formed on the trench top dielectric, which isolates the transistor from the capacitor.

摘要翻译： 一种用于形成垂直晶体管和沟槽电容器的方法。 提供了一种在表面上具有衬垫叠层的半导体衬底和形成在其中的沟槽。 在沟槽的底部形成电容器，暴露沟槽上侧壁的一部分。 然后在电容器上形成导线，随后在沟槽的暴露的侧壁上形成电介质层。 然后通过液相沉积在导线上形成沟槽顶部电介质。 然后在沟槽顶部电介质上形成晶体管，其将晶体管与电容器隔离。

公开(公告)号：US06797564B1

公开(公告)日：2004-09-28

申请号：US10605401

申请日：2003-09-29

申请人： Kuo-Chien Wu ,  Yi-Nan Chen

发明人： Kuo-Chien Wu ,  Yi-Nan Chen

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L27/10885 ,  H01L27/10888

摘要： A method for forming bit lines and bit line contacts in a memory device is provided. A conductive layer is formed over a substrate to cover a plurality of gate structures thereon. A chemical-mechanical polishing operation is performed to polish the conductive layer so that a cap layer of the gate structures is exposed. A portion of the conductive layer is removed so that only the conductive layer between two neighboring gate structures is retained to serve as a bit line contact. A bit line is formed over the substrate such that the bit line and the bit line contact are electrically connected. Because the bit line contact has a smaller dimension compared with a bit line contact formed using the conventional method, the possibility of having a short circuit between a bit line contact and an adjacent bit line is reduced.

摘要翻译： 提供了一种在存储器件中形成位线和位线接触的方法。 导电层形成在衬底上以覆盖其上的多个栅极结构。 进行化学机械抛光操作以抛光导电层，使得栅极结构的盖层暴露。 导电层的一部分被去除，使得仅保持两个相邻栅极结构之间的导电层以用作位线接触。 在衬底上形成位线，使得位线和位线接触电连接。 由于与使用常规方法形成的位线接触相比，位线接触具有较小的尺寸，因此减少了位线接触和相邻位线之间短路的可能性。

公开(公告)号：US06716696B2

公开(公告)日：2004-04-06

申请号：US10206733

申请日：2002-07-26

申请人： Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L28/84

摘要： A method of forming a bottle-shaped trench in a semiconductor substrate. First, the semiconductor substrate is selectively etched to form a trench, wherein the trench has a top portion and a bottom portion. An oxide film is then formed on the top portion of the trench. Next, the semiconductor substrate is etched through the bottom portion of the trench with a diluted ammonia solution as the etchant to form a bottle-shaped trench followed by removal of the oxide film.

摘要翻译： 一种在半导体衬底中形成瓶形沟槽的方法。 首先，选择性地蚀刻半导体衬底以形成沟槽，其中沟槽具有顶部和底部。 然后在沟槽的顶部上形成氧化膜。 接下来，半导体衬底通过沟槽的底部用稀释的氨溶液作为蚀刻剂进行蚀刻，以形成瓶状沟槽，随后除去氧化物膜。