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公开(公告)号：US10256848B2
公开(公告)日：2019-04-09
申请号：US15490021
申请日：2017-04-18
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi Tanaka , Kazuo Watanabe , Tetsuaki Adachi , Masahito Numanami , Yasuhisa Yamamoto
Abstract: A communication unit includes the following elements. A first transmit circuit outputs a first signal or a second signal from a first input signal. A first amplifier amplifies the first signal and outputs a first amplified signal. A first signal generating circuit generates a third signal having a frequency higher than a frequency of the second signal, based on the second signal and a first reference signal. A first filter circuit receives the third signal and allows one of a frequency component representing a sum of the frequency of the second signal and a frequency of the first reference signal and a frequency component representing a difference therebetween to pass through the first filter circuit and attenuates the other one of the frequency components. A second amplifier amplifies the third signal output from the first filter circuit and outputs a second amplified signal.
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公开(公告)号：US10236828B2
公开(公告)日：2019-03-19
申请号：US15684258
申请日：2017-08-23
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kazuma Sugiura , Takashi Yamada , Norio Hayashi , Satoshi Tanaka , Kenichi Shimamoto , Kazuo Watanabe
Abstract: A power amplifier has improved power added efficiency at high output power. The power amplifier includes: a first transistor for amplifying an input signal input to the base thereof and outputting the amplified signal from the collector thereof; a second transistor with power-supply voltage applied to the collector thereof to supply bias voltage or bias current from the emitter thereof to the base of the first transistor; a third transistor whose collector is connected to the collector of the first transistor to amplify the input signal input to the base thereof and output the amplified signal from a collector thereof; a fourth transistor whose base and collector are connected to supply bias from the emitter thereof to the base of the third transistor; and a first resistor with bias control voltage applied to one end thereof and the other end connected to the bases of the second and fourth transistors.
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公开(公告)号：US20190068142A1
公开(公告)日：2019-02-28
申请号：US16112938
申请日：2018-08-27
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Takayuki Tsutsui , Satoshi Tanaka
IPC: H03H7/01 , H03F3/213 , H03F1/52 , H01L23/00 , H01L27/02 , H01L27/06 , H03F3/217 , H03F3/195 , H01L23/66
Abstract: A semiconductor device includes the following elements. A chip has a main surface substantially parallel with a plane defined by first and second directions intersecting with each other. A power amplifier amplifies an input signal and outputs an amplified signal from plural output terminals. First and second filter circuits attenuate harmonics of the amplified signal. The first filter circuit includes a first capacitor connected between the plural output terminals and a ground. The second filter circuit includes a second capacitor connected between the plural output terminals and a ground. On the main surface of the chip, the plural output terminals are disposed side by side in the first direction, and the first capacitor is disposed on a side in the first direction with respect to the plural output terminals, while the second capacitor is disposed on a side opposite the first direction with respect to the plural output terminals.
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公开(公告)号：US10135395B2
公开(公告)日：2018-11-20
申请号：US15821054
申请日：2017-11-22
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi Tanaka , Masatoshi Hase , Yuri Honda , Kazuo Watanabe , Takashi Soga
Abstract: A power amplifier circuit includes a first transistor, a second transistor, a first bias circuit supplying a first bias current or voltage, a second bias circuit supplying a second bias current or voltage, a first inductor, and a first capacitor. A power supply voltage is supplied to a collector of the first transistor, and an emitter thereof is grounded. A radio frequency signal and the first bias current or voltage are supplied to a base of the first transistor. The power supply voltage is supplied to a collector of the second transistor, and an emitter thereof is connected to the collector of the first transistor via the first capacitor and is grounded via the first inductor. The second bias current or voltage is supplied to a base of the second transistor. An amplified radio frequency signal is output from the collector of the second transistor.
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公开(公告)号：US20180287562A1
公开(公告)日：2018-10-04
申请号：US16001658
申请日：2018-06-06
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi Tanaka , Masatoshi Hase , Yuri Honda , Kazuo Watanabe , Takashi Soga
CPC classification number: H03F1/0211 , H03F1/0261 , H03F1/22 , H03F1/56 , H03F1/565 , H03F3/195 , H03F3/213 , H03F3/245 , H03F2200/222 , H03F2200/387 , H03F2200/411 , H03F2200/451 , H03F2200/516
Abstract: A power amplifier circuit includes a first transistor, a second transistor, a first bias circuit supplying a first bias current or voltage, a second bias circuit supplying a second bias current or voltage, a first inductor, and a first capacitor. A power supply voltage is supplied to a collector of the first transistor, and an emitter thereof is grounded. A radio frequency signal and the first bias current or voltage are supplied to a base of the first transistor. The power supply voltage is supplied to a collector of the second transistor, and an emitter thereof is connected to the collector of the first transistor via the first capacitor and is grounded via the first inductor. The second bias current or voltage is supplied to a base of the second transistor. An amplified radio frequency signal is output from the collector of the second transistor.
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Patent Agency Ranking
公开(公告)号：US10069523B2
公开(公告)日：2018-09-04
申请号：US15837499
申请日：2017-12-11
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Takayuki Tsutsui , Satoshi Tanaka , Hidenori Obiya
Abstract: A power amplification module includes a first input terminal arranged to receive a first transmission signal in a first frequency band, a second input terminal arranged to receive a second transmission signal in a second frequency band higher than the first frequency band, a first amplification circuit that amplifies the first transmission signal, a second amplification circuit that amplifies the second transmission signal, a first filter circuit located between the first input terminal and the first amplification circuit, and a second filter circuit located between the second input terminal and the second amplification circuit. The first filter circuit is a low-pass filter that allows the first frequency band to pass therethrough and that attenuates a harmonic of the first transmission signal and the second transmission signal. The second filter circuit is a high-pass filter that allows the second frequency band to pass therethrough and that attenuates the first transmission signal.
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公开(公告)号：US20180213488A1
公开(公告)日：2018-07-26
申请号：US15924861
申请日：2018-03-19
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi Tanaka , Kiichiro Takenaka , Takayuki Tsutsui , Taizo Yamawaki , Shun Imai
CPC classification number: H04W52/246 , H03F1/0216 , H03F1/0227 , H03F1/0277 , H03F3/189 , H03F3/19 , H03F3/21 , H03F3/24 , H03F2200/102 , H03F2200/294 , H03F2200/504 , H04B1/0475 , H04W52/0251 , H04W52/0261 , H04W88/06 , Y02D70/00 , Y02D70/1246 , Y02D70/1262 , Y02D70/40
Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
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公开(公告)号：US10020779B2
公开(公告)日：2018-07-10
申请号：US15251031
申请日：2016-08-30
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kiichiro Takenaka , Masahiro Ito , Masakazu Hori , Mitsuo Ariie , Hayato Nakamura , Satoshi Arayashiki , Hidetoshi Matsumoto , Tsuyoshi Sato , Satoshi Tanaka
IPC: H03F3/191 , H03F1/02 , H03F3/21 , H03F1/32 , H03F1/52 , H03F3/19 , H03F1/56 , H03G3/00 , H03F1/42 , H03F3/04
CPC classification number: H03F1/0222 , H03F1/02 , H03F1/0216 , H03F1/0261 , H03F1/32 , H03F1/42 , H03F1/52 , H03F1/56 , H03F3/04 , H03F3/19 , H03F3/21 , H03F2200/102 , H03F2200/408 , H03F2200/411 , H03F2200/444 , H03F2200/451 , H03G3/004
Abstract: Improvement in linearity is achieved at low costs in a power amplifier module employing an envelope tracking system. The power amplifier module includes a first power amplifier circuit that amplifies a radio frequency signal and that outputs a first amplified signal, a second power amplifier circuit that amplifies the first amplified signal on the basis of a source voltage varying depending on amplitude of the radio frequency signal and that outputs a second amplified signal, and a matching circuit that includes first and second capacitors connected in series between the first and second power amplifier circuit and an inductor connected between a node between the first and second capacitors and a ground and that decreases a gain of the first power amplifier circuit as the source voltage of the second power amplifier circuit increases.
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公开(公告)号：US20180062579A1
公开(公告)日：2018-03-01
申请号：US15656646
申请日：2017-07-21
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi Tanaka , Tetsuaki Adachi , Kazuo Watanabe , Masahito Numanami , Yasuhisa Yamamoto
CPC classification number: H03F1/0205 , H03F1/0261 , H03F1/56 , H03F3/191 , H03F3/193 , H03F3/21 , H03F2200/18 , H03F2200/222 , H03F2200/387 , H03F2200/451 , H03F2200/75
Abstract: Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit.
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公开(公告)号：US20180027503A1
公开(公告)日：2018-01-25
申请号：US15720188
申请日：2017-09-29
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi Tanaka , Kiichiro Takenaka , Takayuki Tsutsui , Taizo Yamawaki , Shun Imai
CPC classification number: H04W52/246 , H03F1/0216 , H03F1/0227 , H03F1/0277 , H03F3/189 , H03F3/19 , H03F3/21 , H03F3/24 , H03F2200/102 , H03F2200/294 , H03F2200/504 , H04B1/0475 , H04W52/0251 , H04W52/0261 , H04W88/06 , Y02D70/00 , Y02D70/1246 , Y02D70/1262 , Y02D70/40
Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
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