公开(公告)号：US12206439B2

公开(公告)日：2025-01-21

申请号：US17818388

申请日：2022-08-09

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takeshi Kogure ,  Kenichi Shimamoto ,  Yoshiki Kogushi ,  Toshiki Matsui

IPC: H04B1/04 ,  H03F1/56 ,  H03F3/24

Abstract: A power amplifier circuit is provided that includes a transmission circuit, a control circuit, a first terminal, and a second terminal. The transmission circuit includes an amplifier element that amplifies power of a radio frequency signal. The control circuit controls the transmission circuit. The first terminal receives a serial data signal that is based on a serial data standard. The second terminal receives a digital signal different from the serial data signal. The control circuit then controls the transmission circuit in response to the digital signal received from the second terminal.

公开(公告)号：US12160207B2

公开(公告)日：2024-12-03

申请号：US17235387

申请日：2021-04-20

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenichi Shimamoto

IPC: H03F3/21 ,  H01L23/66 ,  H03F1/02 ,  H03F1/56

Abstract: A power amplifier includes a first transistor, a second transistor, and a third transistor that are formed on a semiconductor substrate, and a bump that is electrically connected to an emitter of the first transistor and that is provided so as to, when the semiconductor substrate is viewed in plan, overlay a first disposition region where the first transistor is disposed, a second disposition region where the second transistor is disposed, and a third disposition region where the third transistor is disposed.

公开(公告)号：US20170288611A1

公开(公告)日：2017-10-05

申请号：US15629146

申请日：2017-06-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenichi Shimamoto ,  Satoshi Tanaka ,  Tadashi Matsuoka

IPC: H03F1/30 ,  H03F1/02 ,  H03F3/193 ,  H03F3/19 ,  H03F3/24 ,  H03F3/21 ,  H03F1/56

CPC classification number: H03F1/0222 ,  H03F1/0211 ,  H03F1/0261 ,  H03F1/30 ,  H03F1/56 ,  H03F3/19 ,  H03F3/193 ,  H03F3/21 ,  H03F3/245 ,  H03F2200/108 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/387 ,  H03F2200/411 ,  H03F2200/447 ,  H03F2200/451 ,  H03F2200/555

Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.

公开(公告)号：US12273080B2

公开(公告)日：2025-04-08

申请号：US17817018

申请日：2022-08-03

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji Tahara ,  Syunji Yoshimi ,  Kazuhiro Ikarashi ,  Yusuke Tanaka ,  Kenichi Shimamoto ,  Masatoshi Hase

IPC: H03F3/24 ,  H03F1/56 ,  H04B1/04

Abstract: The present disclosure facilitates impedance matching between a power amplifier and filters. A radio-frequency circuit includes a power amplifier, a plurality of transmit filters, a switch, a plurality of first matching networks, and a second matching network. The switch switches the plurality of transmit filters to be coupled to the power amplifier. The plurality of first matching networks are coupled between the plurality of transmit filters and the switch. The second matching network is coupled between the power amplifier and the switch. The second matching network includes a transmission line transformer.

公开(公告)号：US11601102B2

公开(公告)日：2023-03-07

申请号：US17168618

申请日：2021-02-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroaki Tokuya ,  Hideyuki Sato ,  Fumio Harima ,  Kenichi Shimamoto ,  Satoshi Tanaka ,  Takayuki Kawano ,  Ryoki Shikishima ,  Atsushi Kurokawa

IPC: H03F1/30 ,  H03F3/24 ,  H01L23/00 ,  H03F3/195

Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor disposed on the semiconductor substrate and configured to supply a bias current based on a first current which is a part of a control current to the first transistor; a third transistor disposed on the semiconductor substrate and having a collector configured to be supplied with a second current which is a part of the control current and an emitter configured to output a third current based on the second current; a first bump electrically connected to an emitter of the first transistor and disposed so as to overlap a first disposition area in which the first transistor is disposed in plan view of the semiconductor substrate; and a second bump disposed so as to overlap a second disposition area in which the third transistor is disposed in the plan view.

公开(公告)号：US10211073B2

公开(公告)日：2019-02-19

申请号：US15849065

申请日：2017-12-20

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenichi Shimamoto

IPC: H01L21/56 ,  H01L23/00 ,  H03F3/195 ,  H01L23/498

Abstract: A semiconductor chip has a first transistor that amplifies a first signal and outputs a second signal, a second transistor that amplifies the second signal and outputs a third signal, and a semiconductor substrate having a main surface parallel to a plane defined by first and second directions and which has the first and second transistors formed thereon. The main surface has thereon a first bump connected to a collector or drain of the first transistor, a second bump connected to an emitter or source of the first transistor, a third bump connected to a collector or drain of the second transistor, and a fourth bump connected to an emitter or source of the second transistor. The first bump is circular, the second through fourth bumps are rectangular or oval, and the area of each of the second through fourth bumps is larger than that of the first bump.

公开(公告)号：US10003307B2

公开(公告)日：2018-06-19

申请号：US15673811

申请日：2017-08-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji Sasaki ,  Kenichi Shimamoto

IPC: H01L21/00 ,  H03F1/30 ,  H01L27/082 ,  H01L23/00 ,  H01L23/367 ,  H01L27/02 ,  H03F3/193 ,  H03F3/21

CPC classification number: H03F1/301 ,  H01L23/367 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L27/0248 ,  H01L27/082 ,  H01L2224/13013 ,  H01L2224/1403 ,  H01L2224/1415 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17519 ,  H03F3/193 ,  H03F3/21 ,  H03F2200/451 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor substrate having a principal surface which has a first side in a first direction and a second side in a second direction. A plurality of transistor arrays is formed in a region adjacent to the first side of the semiconductor substrate. A plurality of bumps include first and second bumps which are longer in the first direction. The distance between the first side and the first bump is shorter than the distance between the first side and the second bump. The plurality of transistor arrays include a first and a second transistor arrays. The first transistor array has a plurality of first unit transistors arranged along the first direction such that the first unit transistors overlap the first bump. The second transistor array has a plurality of second unit transistors arranged along the first direction such that the second unit transistors overlap the second bump.

公开(公告)号：US09768729B2

公开(公告)日：2017-09-19

申请号：US14862865

申请日：2015-09-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuma Sugiura ,  Takashi Yamada ,  Norio Hayashi ,  Satoshi Tanaka ,  Kenichi Shimamoto ,  Kazuo Watanabe

IPC: H03F3/68 ,  H03F1/02 ,  H03F3/19 ,  H03F3/21 ,  H03F3/24

CPC classification number: H03F1/0205 ,  H03F1/0222 ,  H03F3/19 ,  H03F3/211 ,  H03F3/245 ,  H03F2200/451 ,  H03F2200/516 ,  H03F2200/555

Abstract: A power amplifier has improved power added efficiency at high output power. The power amplifier includes: a first transistor for amplifying an input signal input to the base thereof and outputting the amplified signal from the collector thereof; a second transistor with power-supply voltage applied to the collector thereof to supply bias voltage or bias current from the emitter thereof to the base of the first transistor; a third transistor whose collector is connected to the collector of the first transistor to amplify the input signal input to the base thereof and output the amplified signal from a collector thereof; a fourth transistor whose base and collector are connected to supply bias from the emitter thereof to the base of the third transistor; and a first resistor with bias control voltage applied to one end thereof and the other end connected to the bases of the second and fourth transistors.

公开(公告)号：US12199573B2

公开(公告)日：2025-01-14

申请号：US16923493

申请日：2020-07-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenichi Shimamoto

IPC: H03F1/52 ,  H03F1/56 ,  H03F3/21

Abstract: A power amplifier circuit includes a first amplifier that amplifies an input signal and outputs a first amplified signal, a second amplifier that is disposed subsequent to the first amplifier and that amplifies the first amplified signal and outputs a second amplified signal, and a clamp circuit that is disposed between ground and a signal line extending between the first amplifier and the second amplifier and that suppresses an amplitude of the first amplified signal.

公开(公告)号：US20220294401A1

公开(公告)日：2022-09-15

申请号：US17805259

申请日：2022-06-03

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Kenji Tahara ,  Kenichi Shimamoto ,  Yusuke Tanaka

IPC: H03F3/24 ,  H03F3/195 ,  H03F1/02

Abstract: Increase in power-added efficiency can be achieved. A second base of a second transistor is connected to a first collector of a first transistor. A third base of a third transistor is connected to the first collector of the first transistor, and a third collector of the third transistor is connected to a second collector of the second transistor. A second bias circuit includes a fifth transistor connected to the second base of the second transistor. A third bias circuit includes a sixth transistor connected to the third base of the third transistor. A first current limiting circuit includes a seventh transistor, a first collector resistor, and a first base resistor. A second current limiting circuit includes an eighth transistor, a second collector resistor, and a second base resistor.