Method of making a metal-insulator-metal capacitor in the CMOS process
    81.
    发明授权
    Method of making a metal-insulator-metal capacitor in the CMOS process 有权
    在CMOS工艺中制作金属 - 绝缘体 - 金属电容器的方法

    公开(公告)号:US07294544B1

    公开(公告)日:2007-11-13

    申请号:US09249254

    申请日:1999-02-12

    IPC分类号: H01L21/336

    摘要: A method for fabricating an improved metal-insulator-metal capacitor is achieved. An insulating layer is provided overlying conducting lines on a semiconductor substrate. Via openings through the insulating layer to the conducting lines are filled with metal plugs. A first metal layer is deposited overlying the insulating layer and the metal plugs. A capacitor dielectric layer is deposited overlying the first metal layer wherein capacitor dielectric layer is deposited as a dual layer, each layer deposited within a separate chamber whereby pinholes are eliminated. A second metal layer and a barrier metal layer are deposited overlying the capacitor dielectric layer. The second metal layer and the barrier metal layer are patterned to form a top plate electrode. Thereafter, the capacitor dielectric layer and the first metal layer are patterned to form a bottom plate electrode completing fabrication of a metal-insulator-metal capacitor.

    摘要翻译: 实现了一种制造改进的金属 - 绝缘体 - 金属电容器的方法。 在半导体衬底上覆盖导电线的绝缘层。 通过绝缘层到导线的开口填充有金属插头。 沉积在绝缘层和金属插头上的第一金属层。 电容器电介质层沉积在第一金属层上,其中电容器电介质层被沉积为双层,每层沉积在单独的室内,由此消除针孔。 沉积在电容器介电层上的第二金属层和阻挡金属层。 将第二金属层和阻挡金属层图案化以形成顶板电极。 此后,对电容器电介质层和第一金属层进行图案化以形成完成金属 - 绝缘体 - 金属电容器的制造的底板电极。

    Method of forming silicided gate structure
    82.
    发明授权
    Method of forming silicided gate structure 有权
    形成硅化栅结构的方法

    公开(公告)号:US07241674B2

    公开(公告)日:2007-07-10

    申请号:US10846278

    申请日:2004-05-13

    IPC分类号: H01L21/3205 H01L21/336

    CPC分类号: H01L29/66507 H01L21/28097

    摘要: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

    摘要翻译: 提供了在具有活性区域的基板上形成硅化栅的方法。 该方法包括在有源区和栅极的一部分上形成硅化物,留下栅极的剩余部分未被硅化; 在成形步骤之后在有源区和栅上形成屏蔽层; 在所述有源区上的所述屏蔽层的部分上形成涂层; 打开所述屏蔽层以暴露所述栅极,其中所述涂层在所述打开步骤期间保护所述屏蔽层的所述部分在所述有源区域上方; 在暴露的栅极上沉积金属层; 并退火以使金属与栅极反应,使栅极的剩余部分的至少一部分硅化。

    Hybrid STI stressor with selective re-oxidation anneal

    公开(公告)号:US20070148881A1

    公开(公告)日:2007-06-28

    申请号:US11320221

    申请日:2005-12-28

    IPC分类号: H01L21/336

    摘要: A method for forming stressors in a semiconductor substrate is provided. The method includes providing a semiconductor substrate including a first device region and a second device region, forming shallow trench isolation (STI) regions with a high-shrinkage dielectric material in the first and the second device regions wherein the STI regions define a first active region in the first device region and a second active region in the second device region, forming an insulation mask over the STI region and the first active region in the first device region wherein the insulation mask does not extend over the second device region, and performing a stress-tuning treatment to the semiconductor substrate. The first active region and second active region have tensile stress and compressive stress respectively. An NMOS and a PMOS device are formed on the first and second active regions, respectively.

    Multiple gate field effect transistor structure
    85.
    发明申请
    Multiple gate field effect transistor structure 有权
    多栅场效应晶体管结构

    公开(公告)号:US20060180854A1

    公开(公告)日:2006-08-17

    申请号:US11057423

    申请日:2005-02-14

    IPC分类号: H01L31/113

    摘要: A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel spaced apart sidewall portions, each of said sidewall portions comprising major inner and outer surfaces and an upper surface; wherein, each of said surfaces comprises a surface for forming an overlying field effect transistor (FET).

    摘要翻译: 一种用于形成多达6个FET器件的多栅极区域FET器件及其形成方法,该器件包括多个鳍状结构,其包括设置在衬底上的半导体材料; 所述多个鳍状结构包括基本上平行的间隔开的侧壁部分,每个所述侧壁部分包括主要内表面和外表面以及上表面; 其中,每个所述表面包括用于形成上覆场效应晶体管(FET)的表面。

    Low oxygen content photoresist stripping process for low dielectric constant materials
    86.
    发明授权
    Low oxygen content photoresist stripping process for low dielectric constant materials 失效
    低介电常数材料的低含氧光刻胶剥离工艺

    公开(公告)号:US07029992B2

    公开(公告)日:2006-04-18

    申请号:US10920099

    申请日:2004-08-17

    IPC分类号: H01L21/322

    CPC分类号: H01L21/31138 G03F7/427

    摘要: A plasma containing 5–10% oxygen and 90–95% of an inert gas strips photoresist from over a low-k dielectric material formed on or in a semiconductor device. The inert gas may be nitrogen, hydrogen, or a combination thereof, or it may include at least one of nitrogen, hydrogen, NH3, Ar, He, and CF4. The operating pressure of the plasma may range from 1 millitorr to 150 millitor. The plasma removes photoresist, the hard skin formed on photoresist during aggressive etch processes, and polymeric depositions formed during etch processes. The plasma strips photoresist at a rate sufficiently high for production use and does not appreciably attack carbon-containing low-k dielectric materials. An apparatus including a plasma tool containing a semiconductor substrate and the low oxygen-content plasma, is also provided.

    摘要翻译: 含有5-10%氧气和90-95%惰性气体的等离子体从形成在半导体器件上或半导体器件中的低k电介质材料上剥离光致抗蚀剂。 惰性气体可以是氮气,氢气或它们的组合,或者它可以包括氮气,氢气,NH 3,Ar,He和CF 4中的至少一种。 。 等离子体的工作压力可以在1毫托至150毫升之间。 等离子体去除光致抗蚀剂,在腐蚀性蚀刻工艺期间在光致抗蚀剂上形成的硬皮以及在蚀刻工艺期间形成的聚合物沉积。 等离子体以足够高的生产用途的速率剥离光致抗蚀剂,并且不会明显地攻击含碳低k电介质材料。 还提供了包括含有半导体衬底和低含氧等离子体的等离子体工具的装置。

    Seal ring design without stop layer punch through during via etch
    87.
    发明申请
    Seal ring design without stop layer punch through during via etch 审中-公开
    密封圈设计,无停止层通孔蚀刻过程中

    公开(公告)号:US20050184388A1

    公开(公告)日:2005-08-25

    申请号:US10782365

    申请日:2004-02-19

    IPC分类号: H01L23/48 H01L23/58

    摘要: In accordance with the objective of the invention a new method is provided for the creation of a seal ring having dissimilar elements. The Critical Dimensions of the seal ring are selected with respect to the CD of other device features, such a seal vias, such that the difference in etch sensitivity between the created seal ring and the via holes is removed. All etch of the simultaneously etched features is completed at the same time, avoiding punch through of an underlying layer of etch stop material.

    摘要翻译: 根据本发明的目的,提供了一种用于创建具有不同元件的密封环的新方法。 密封环的临界尺寸相对于其它装置特征(例如密封通孔)的CD被选择,使得所产生的密封环和通孔之间的蚀刻敏感性的差异被去除。 同时蚀刻的特征的所有蚀刻同时完成,避免冲蚀下一层蚀刻停止材料。

    Process for patterning high-k dielectric material
    88.
    发明申请
    Process for patterning high-k dielectric material 有权
    图案化高k电介质材料的工艺

    公开(公告)号:US20050181590A1

    公开(公告)日:2005-08-18

    申请号:US11101774

    申请日:2005-04-08

    CPC分类号: H01L21/31144 H01L21/31116

    摘要: A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method further includes a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.

    摘要翻译: 提供了一种图案化高k介电材料层的方法,其可用于制造半导体器件。 在高k电介质层上进行第一蚀刻。 在第一蚀刻之后,用第一蚀刻蚀刻的高k电介质层的一部分保留。 执行高k电介质层的第二蚀刻以去除高k电介质层的剩余部分。 第二蚀刻不同于第一蚀刻。 优选地,第一蚀刻是干蚀刻工艺,第二蚀刻是湿蚀刻工艺。 该方法还包括在第一次蚀刻之后和第二次蚀刻之前等离子体灰化高k电介质层的剩余部分的工艺。

    Method to form a metal silicide gate device
    89.
    发明申请
    Method to form a metal silicide gate device 失效
    形成金属硅化物栅极器件的方法

    公开(公告)号:US20050179098A1

    公开(公告)日:2005-08-18

    申请号:US10780513

    申请日:2004-02-17

    摘要: A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidewalls of the polysilicon lines. The first isolation layer does not overlie the top surface of the polysilicon lines. The polysilicon lines are partially etched down such that the top surfaces of the polysilicon lines are below the top surface of the first isolation layer. A metal layer is deposited overlying the polysilicon lines. A thermal anneal is used to completely convert the polysilicon lines to metal silicide gates. The unreacted metal layer is removed to complete the device.

    摘要翻译: 实现了在制造集成电路器件中形成金属硅化物栅极的新方法。 该方法包括在其间具有介电层的衬底上形成多晶硅线。 第一隔离层形成在衬底和多晶硅线的侧壁上。 第一隔离层不覆盖多晶硅线的顶表面。 多晶硅线被部分地向下蚀刻,使得多晶硅线的顶表面在第一隔离层的顶表面下方。 金属层沉积在多晶硅线上。 使用热退火将多晶硅线完全转换成金属硅化物栅极。 去除未反应的金属层以完成该装置。