公开(公告)号：US11545980B1

公开(公告)日：2023-01-03

申请号：US17469811

申请日：2021-09-08

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu Lee ,  Jeffrey Charles Lee ,  George Alan Wiley

IPC: H03L7/00 ,  H03L7/08 ,  H03K3/037 ,  H03L7/081

Abstract: An apparatus has a plurality of multi-level comparison circuits, each coupled to a pair of wires in a three-wire communication link, a plurality of first-level clock recovery circuits and a second-level clock recovery circuit. Each multi-level comparison circuit provides a multibit signal as an output. Each first-level clock recovery circuit includes a plurality of first-level flipflops clocked by transitions in a multibit signal received from one multi-level comparison circuit of the plurality of multi-level comparison circuits, and a first delay circuit that delays an output of the each first-level clock recovery circuit to provide a first reset signal that resets the each first-level clock recovery circuit. The second-level clock recovery circuit includes a second-level flipflop clocked by transitions in the outputs of the plurality of first-level clock recovery circuits, and a second delay circuit that delays an output of the second-level clock recovery circuit to provide a second reset signal to the second-level flipflop.

公开(公告)号：US10587391B2

公开(公告)日：2020-03-10

申请号：US16218936

申请日：2018-12-13

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley

IPC: H04L7/00 ,  H04L5/02 ,  H04L27/26 ,  H04B3/54 ,  G06F13/40 ,  G06F13/42 ,  H04L12/40 ,  H04L25/02

Abstract: Systems, methods and apparatus are described that facilitate transmission of data between two devices within an electronic apparatus. A data transfer method includes receiving from a three-wire interface, a first packet of data encoded in a first sequence of symbols representing transitions in signaling state of the three wires, and transmitting on the three-wire interface, a second packet of data encoded in a second sequence of symbols representing transitions in signaling state of the three wires. The first sequence of symbols may include up to five types of symbol. The second sequence of symbols may include two or three types of symbol.

公开(公告)号：US10353837B2

公开(公告)日：2019-07-16

申请号：US15087535

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  Richard Dominic Wietfeldt ,  George Alan Wiley

IPC: G06F13/364 ,  G06F13/42 ,  G06F13/26 ,  G06F13/24 ,  G06F13/36 ,  G06F13/362 ,  G06F11/30

Abstract: To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to assert an in-band IRQ. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.

公开(公告)号：US20190215137A1

公开(公告)日：2019-07-11

申请号：US16218936

申请日：2018-12-13

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley

IPC: H04L5/02 ,  H04L27/26 ,  H04B3/54 ,  H04L7/00

Abstract: Systems, methods and apparatus are described that facilitate transmission of data between two devices within an electronic apparatus. A data transfer method includes receiving from a three-wire interface, a first packet of data encoded in a first sequence of symbols representing transitions in signaling state of the three wires, and transmitting on the three-wire interface, a second packet of data encoded in a second sequence of symbols representing transitions in signaling state of the three wires. The first sequence of symbols may include up to five types of symbol. The second sequence of symbols may include two or three types of symbol.

公开(公告)号：US10134272B2

公开(公告)日：2018-11-20

申请号：US15649178

申请日：2017-07-13

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley ,  Glenn D. Raskin

IPC: G08C19/12 ,  G08C19/16 ,  H04L25/02

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as N-phase polarity encoded symbols or as packets on differentially driven connectors. A data transfer method comprises encoding data and control signals in a sequence of symbols to be transmitted on a plurality of connectors, and transmitting the sequence of symbols on the plurality of connectors. Each symbol may be transmitted using a combination of a phase state of a first pair of connectors, a polarity of a second pair of connectors, and a selection of at least one undriven connector. Transmission of each symbol in the sequence of symbols may cause a change of state for at least one of the plurality of connectors.

公开(公告)号：US10128964B2

公开(公告)日：2018-11-13

申请号：US15454608

申请日：2017-03-09

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley

IPC: H04B17/21 ,  H04L25/03 ,  H04L7/10 ,  H04L25/14 ,  H04L25/49

Abstract: Methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. In particular, a preamble for transmission in a sequence of symbols over a multi-wire communications interface, such as a MIPI C-PHY interface, is constructed to include one or more symbols each having a single state transition symbols for signaling a particular calibration preamble from a transmitter to a receiver over the multi-wire communications interface. The preamble, having only single state transition symbols, improves reliability of decoding the symbols at a receiver, including reception and decoding without the use of a calibration clock.

公开(公告)号：US10033560B2

公开(公告)日：2018-07-24

申请号：US15703878

申请日：2017-09-13

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley

IPC: H04L25/34 ,  H04L25/49 ,  H04L25/02 ,  H04L27/22 ,  H04L7/033 ,  H04L5/20

CPC classification number: H04L25/4917 ,  H04L5/20 ,  H04L7/033 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298 ,  H04L27/22

Abstract: A high-speed serial interface is provided. In one aspect, the high-speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high-speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high-speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

公开(公告)号：US09921981B2

公开(公告)日：2018-03-20

申请号：US14462363

申请日：2014-08-18

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  Richard Dominic Wietfeldt ,  George Alan Wiley

IPC: G06F13/22 ,  G06F13/24 ,  G06F13/26 ,  G06F13/42

CPC classification number: G06F13/4226 ,  G06F13/22 ,  G06F13/24 ,  G06F13/26 ,  G06F2211/001 ,  G06F2211/002

Abstract: A master device is provided which is coupled to a shared single line interrupt request (IRQ) bus and a control data bus. The master device group slave devices coupled to the shared single line IRQ bus into one or more groups, where each group is associated with a different IRQ signal. The master device then monitors the IRQ bus to ascertain when an IRQ signal is asserted by at least one slave device. The master device then identifies a group to with which the IRQ signal is associated. The slave devices for the identified group are then scanned or queried by the master device to ascertain which slave device asserted the IRQ signal on the IRQ bus. Each group uses a distinguishable IRQ signal to allow the master device to ascertain which group to query or scan.

公开(公告)号：US09832094B2

公开(公告)日：2017-11-28

申请号：US14666018

申请日：2015-03-23

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley

IPC: G01R33/14 ,  H04L12/26 ,  G01R31/319 ,  G01R31/317 ,  H04B1/10 ,  H04B3/46 ,  H04L25/02 ,  H04L25/14 ,  H04B3/462 ,  G06N3/00 ,  H04L25/49

CPC classification number: H04L43/087 ,  G01R31/31708 ,  G01R31/31901 ,  G06K2207/00 ,  G06N3/00 ,  G06T2200/00 ,  H04B1/1081 ,  H04B3/46 ,  H04B3/462 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/4923

Abstract: A measurement task is selected, where the measurement task is associated with a transmission of an encoded signal transmitted via a plurality of data lines. The encoded signal is encoded using one or more of 3-Phase, N-Phase, or N-factorial low-voltage differential signaling (LVDS) where N is at least three (3). A repeating waveform is generated corresponding to the measurement task. The repeating waveform corresponding to the measurement task is then transmitted via the plurality of data lines.

公开(公告)号：US20170329738A1

公开(公告)日：2017-11-16

申请号：US15589805

申请日：2017-05-08

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  George Alan Wiley

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38

CPC classification number: G06F13/4286 ,  G06F13/38 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4213

Abstract: Systems, methods, and apparatus for line multiplexed serial interfaces are disclosed. A method performed by a transmitting device includes asserting a stop condition on a wire of a serial data link by driving the wire to a first voltage level for a first period of time that is less than a duration of the stop condition, monitoring the wire after the first period of time, determining that flow-control has been asserted when the wire remains at a second voltage level for a second period of time that exceeds a minimum period of time defined for flow-control pulses and after the first period of time has elapsed, refraining from transmitting data on the wire while flow-control is asserted, and transmitting data on the wire when flow-control is de-asserted.