公开(公告)号：US20120168709A1

公开(公告)日：2012-07-05

申请号：US13419522

申请日：2012-03-14

申请人： Matthew J. Breitwisch ,  Chandrasekharan Kothandaraman ,  Chung H. Lam

发明人： Matthew J. Breitwisch ,  Chandrasekharan Kothandaraman ,  Chung H. Lam

IPC分类号： H01L45/00

CPC分类号： H01L45/148 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1683

摘要： A method of fabricating a phase change memory element within a semiconductor structure includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region at a same layer within the semiconductor structure, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material.

摘要翻译： 在半导体结构内制造相变存储元件的方法包括蚀刻到底部电极的上表面的开口，该开口由等于半导体结构内同一层的金属区域的高度的高度形成， 在开口内沉积相变材料，使开关内的相变材料凹陷，并在凹陷相变材料上形成顶部电极。

公开(公告)号：US20120012977A1

公开(公告)日：2012-01-19

申请号：US12835764

申请日：2010-07-14

申请人： Yan Zun Li ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

发明人： Yan Zun Li ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse is provided having a unitary monocrystalline semiconductor body including first and second semiconductor regions each having the same first conductivity type, and a third semiconductor region between the first and second semiconductor regions which has a second conductivity type opposite from the first conductivity type. An anode and a cathode can be electrically connected with the first semiconductor region. A conductive region including a metal, a conductive compound of a metal or an alloy of a metal can contact the first semiconductor region and extend between the cathode and the anode. The antifuse can further include a contact electrically connected with the second semiconductor region. In this way, the antifuse can be configured such that the application of a programming voltage between the anode and the cathode heats the first semiconductor region sufficiently to reach a temperature which drives a dopant outwardly therefrom, causing an edge of the first semiconductor region to move closer to an adjacent edge of the second semiconductor region, thus permanently reducing electrical resistance between the first and second semiconductor regions by one or more orders of magnitude.

摘要翻译： 提供一种具有单一单晶半导体本体的反熔丝，该单体半导体本体包括具有相同的第一导电类型的第一和第二半导体区域以及具有与第一导电类型相反的第二导电类型的第一和第二半导体区域之间的第三半导体区域。 阳极和阴极可以与第一半导体区域电连接。 包括金属，金属的导电化合物或金属的合金的导电区域可以接触第一半导体区域并在阴极和阳极之间延伸。 反熔丝还可以包括与第二半导体区域电连接的触点。 以这种方式，反熔丝可被配置为使得在阳极和阴极之间施加编程电压将第一半导体区域充分加热以达到从其向外驱动掺杂剂的温度，从而使第一半导体区域的边缘移动 更靠近第二半导体区域的相邻边缘，从而将第一和第二半导体区域之间的电阻永久地减小一个或多个数量级。

公开(公告)号：US08004060B2

公开(公告)日：2011-08-23

申请号：US11946938

申请日：2007-11-29

申请人： Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran ,  Kenneth J. Stein

发明人： Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran ,  Kenneth J. Stein

IPC分类号： H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.

摘要翻译： 金属层和半导体层顺序地沉积在基板上。 半导体层和金属层被光刻图案化以形成半导体部分和金属栅极部分的堆叠，其优选地与至少一个金属栅极叠层的形成同时进行。 在一个实施例中，半导体部分的尺寸减小，并且金属半导体合金部分通过金属化形成在半导体部分上。 在由此形成的第一电反熔丝中，金属半导体合金部分可以电铸以在金属半导体合金部分和金属栅极部分之间形成短路。 在另一个实施例中，在半导体部分上形成两个非接合的金属半导体合金部分。 在由此形成的第二电反熔丝中，金属半导体合金部分可以被电铸以在两个先前接合的金属半导体合金部分之间形成短路。

公开(公告)号：US20090283840A1

公开(公告)日：2009-11-19

申请号：US12119526

申请日：2008-05-13

申请人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Ephrem G. Gebreselasie ,  Zhong-Xiang He ,  Herbert Lei Ho ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Robert Mark Rassel ,  John Matthew Safran ,  Kenneth Jay Stein ,  Norman Whitelaw Robson ,  Ping-Chuan Wang ,  Hongwen Yan

发明人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Ephrem G. Gebreselasie ,  Zhong-Xiang He ,  Herbert Lei Ho ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Robert Mark Rassel ,  John Matthew Safran ,  Kenneth Jay Stein ,  Norman Whitelaw Robson ,  Ping-Chuan Wang ,  Hongwen Yan

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

摘要翻译： 半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成 部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。 场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。 熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料 栅电极。

公开(公告)号：US20090141533A1

公开(公告)日：2009-06-04

申请号：US11946938

申请日：2007-11-29

申请人： Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran ,  Kenneth J. Stein

发明人： Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran ,  Kenneth J. Stein

IPC分类号： G11C17/08 ,  H01L27/20 ,  H01L21/768

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.

摘要翻译： 金属层和半导体层顺序地沉积在基板上。 半导体层和金属层被光刻图案化以形成半导体部分和金属栅极部分的堆叠，其优选地与至少一个金属栅极叠层的形成同时进行。 在一个实施例中，半导体部分的尺寸减小，并且金属半导体合金部分通过金属化形成在半导体部分上。 在由此形成的第一电反熔丝中，金属半导体合金部分可以电铸以在金属半导体合金部分和金属栅极部分之间形成短路。 在另一个实施例中，在半导体部分上形成两个非接合的金属半导体合金部分。 在由此形成的第二电反熔丝中，金属半导体合金部分可以被电铸以在两个先前接合的金属半导体合金部分之间形成短路。

公开(公告)号：US20090108396A1

公开(公告)日：2009-04-30

申请号：US11925164

申请日：2007-10-26

申请人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman

发明人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman

IPC分类号： H01L29/86 ,  H01L21/71

CPC分类号： H01L23/5256 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.

摘要翻译： 在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。 连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。 蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。 去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。 形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。 在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

公开(公告)号：US20090101989A1

公开(公告)日：2009-04-23

申请号：US11874385

申请日：2007-10-18

申请人： Xiangdong Chen ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

发明人： Xiangdong Chen ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

IPC分类号： H01L27/06 ,  H01L21/3205

CPC分类号： H01L27/0617 ,  H01L23/5256 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.

摘要翻译： 在用于金属栅电极的金属栅极层上形成电介质材料层，然后通过光刻图案形成电介质材料部分，随后在其上形成多晶半导体层。 在包含金属栅极层和多晶半导体层的垂直邻接堆叠的半导体基板的区域中形成采用金属栅电极的半导体器件。 形成有电熔丝形状的材料堆叠形成在半导体衬底的另一区域中，该区域包含金属栅极层，电介质材料部分和多晶半导体层的垂直叠层。 在多晶半导体层的金属化之后，在将电熔丝与金属栅极层分离开的电介质材料部分上形成包含多晶半导体部分和金属半导体合金部分的电熔丝。

公开(公告)号：US20090065761A1

公开(公告)日：2009-03-12

申请号：US11850742

申请日：2007-09-06

申请人： Kuang-Neng Chen ,  Bruce G. Elmegreen ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman ,  Chung Hon Lam ,  Lia Krusin-Elbaum ,  Dennis M. Newns ,  Byeongju Park ,  Sampath Purushothaman

发明人： Kuang-Neng Chen ,  Bruce G. Elmegreen ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman ,  Chung Hon Lam ,  Lia Krusin-Elbaum ,  Dennis M. Newns ,  Byeongju Park ,  Sampath Purushothaman

IPC分类号： H01L47/00 ,  H01L21/82

CPC分类号： H01L23/5256 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

摘要： A programmable phase change material (PCM) structure includes a heater element formed at a BEOL level of a semiconductor device, the BEOL level including a low-K dielectric material therein; a first via in electrical contact with a first end of the heater element and a second via in electrical contact with a second end of the heater element, thereby defining a programming current path which passes through the first via, the heater element, and the second via; a PCM element disposed above the heater element, the PCM element configured to be programmed between a lower resistance crystalline state and a higher resistance amorphous state through the use of programming currents through the heater element; and a third via in electrical contact with the PCM element, thereby defining a sense current path which passes through the third via, the PCM element, the heater element, and the second via.

摘要翻译： 可编程相变材料（PCM）结构包括形成在半导体器件的BEOL级的加热器元件，BEOL级包括其中的低K电介质材料; 与加热器元件的第一端电接触的第一通孔和与加热器元件的第二端电接触的第二通孔，从而限定通过第一通孔，加热元件和第二通孔的编程电流通路 通过; 设置在所述加热器元件上方的PCM元件，所述PCM元件被配置为通过使用通过所述加热器元件的编程电流在较低电阻结晶状态和较高电阻非晶态之间被编程; 以及与PCM元件电接触的第三通孔，从而限定穿过第三通孔，PCM元件，加热器元件和第二通孔的感测电流路径。

公开(公告)号：US07436044B2

公开(公告)日：2008-10-14

申请号：US11306597

申请日：2006-01-04

申请人： Babar A. Khan ,  Chandrasekharan Kothandaraman ,  Kai Xiu

发明人： Babar A. Khan ,  Chandrasekharan Kothandaraman ,  Kai Xiu

IPC分类号： H01L29/00

CPC分类号： H01L29/42384 ,  H01L23/345 ,  H01L23/5256 ,  H01L29/78669 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to electrical fuses that each comprises at least one thin film transistor. In one embodiment, the electrical fuse of the present invention comprises a hydrogenated thin film transistor with an adjacent heating element. Programming of such an electrical fuse can be effectuated by heating the hydrogenated thin film transistor so as to cause at least partial dehydrogenation. Consequentially, the thin film transistor exhibits detectible physical property change(s), which defines a programmed state. In an alternative embodiment of the present invention, the electrical fuse comprises a thin film transistor that is either hydrogenated or not hydrogenated. Programming of such an alternative electrical fuse can be effectuated by applying a sufficient high back gate voltage to the thin film transistor to cause state changes in the channel-gate interface. In this manner, the thin film transistor also exhibits detectible property change(s) to define a programmed state.

摘要翻译： 本发明涉及电熔丝，每个电熔丝包括至少一个薄膜晶体管。 在一个实施例中，本发明的电熔丝包括具有相邻加热元件的氢化薄膜晶体管。 可以通过加热氢化薄膜晶体管来实现这种电熔丝的编程，从而至少部分脱氢。 因此，薄膜晶体管表现出可检测的物理特性变化，其定义了编程状态。 在本发明的替代实施例中，电熔丝包括被氢化或未氢化的薄膜晶体管。 可以通过向薄膜晶体管施加足够的高背栅电压来引起通道栅极界面的状态变化来实现这种替代电熔丝的编程。 以这种方式，薄膜晶体管还具有可检测的特性变化以限定编程状态。

公开(公告)号：US20080170457A1

公开(公告)日：2008-07-17

申请号：US11622614

申请日：2007-01-12

申请人： Chandrasekharan Kothandaraman

发明人： Chandrasekharan Kothandaraman

IPC分类号： H03K17/18

CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for sensing an electrical signal includes the steps of: providing an arrangement having a fuse connected in series to an antifuse, the arrangement further having an output tap connected to an intermediate node located between the fuse and the antifuse; programming the fuse and the antifuse; applying a sense signal across the combination of the programmed fuse and the programmed antifuse, and then measuring an output signal at the output tap.

摘要翻译： 一种用于感测电信号的方法包括以下步骤：提供具有与反熔丝串联连接的熔丝的布置，该布置还具有连接到位于熔丝和反熔丝之间的中间节点的输出抽头; 编程保险丝和反熔丝; 在编程的熔丝和编程的反熔丝的组合之间应用感测信号，然后在输出抽头测量输出信号。