公开(公告)号：US09252023B2

公开(公告)日：2016-02-02

申请号：US13234975

申请日：2011-09-16

Applicant: Shih-Hung Chen ,  Chien-An Chen ,  Ying Xiao ,  Ying Zhang

Inventor： Shih-Hung Chen ,  Chien-An Chen ,  Ying Xiao ,  Ying Zhang

IPC: H01L21/44 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31138 ,  H01L21/31116 ,  H01L21/76802

Abstract: An etching method comprises etching an oxide layer with a first dc bias of a plasma chamber, removing a photoresist layer with a second dc bias of the plasma chamber and etching through a liner film with a third dc bias of the plasma chamber. In order to reduce the copper deposition on the wall of the plasma chamber, the third dc bias is set to be less than the first and second dc bias.

Abstract translation: 蚀刻方法包括用等离子体室的第一直流偏压蚀刻氧化物层，用等离子体室的第二直流偏压去除光致抗蚀剂层，并通过具有等离子体室的第三直流偏压的衬垫膜进行蚀刻。 为了减少等离子体室壁上的铜沉积，将第三直流偏压设定为小于第一和第二直流偏压。

公开(公告)号：US09140976B2

公开(公告)日：2015-09-22

申请号：US13619124

申请日：2012-09-14

Applicant: Chih-Chang Hsieh ,  Shih-Hung Chen ,  Hang-Ting Lue

Inventor： Chih-Chang Hsieh ,  Shih-Hung Chen ,  Hang-Ting Lue

IPC: G03F1/00 ,  G03F1/36 ,  G11C5/06 ,  G03F1/38 ,  G11C5/02

CPC classification number: G03F1/36 ,  G03F1/38 ,  G11C5/025 ,  G11C5/063

Abstract: A lithography mask and method for manufacturing such mask that includes optically isolated via features and proximity correction features. The via patterns that include via features that define vias are positioned on the mask in rows and columns with a row and a column pitch between each row and column on the mask. The via patterns are positioned such that via features that are in adjacent columns are separated by at least one intervening row between them. The via patterns can also be positioned such that the via patterns that are in adjacent rows are separated by at least one intervening column between them. As a result, the via feature of each via pattern and the associated optical proximity correction features that are positioned around each via feature do not overlap with the optical proximity correction features and the via features of the surrounding via patterns.

Abstract translation: 一种光刻掩模和用于制造这种掩模的方法，其包括光学隔离的特征和接近校正特征。 包括定义通孔的通孔特征的通孔图案以掩模上每行和列之间的行和列间距的行和列定位在掩模上。 通孔图案被定位成使得相邻列中的通孔特征由它们之间的至少一个中间行分开。 通孔图案也可以被定位成使得相邻行中的通孔图案被它们之间的至少一个中间柱隔开。 结果，每个通孔图案的通孔特征和位于每个通孔特征周围的相关联的光学邻近校正特征不与周围通孔图案的光学邻近校正特征和通孔特征重叠。

公开(公告)号：US09035369B2

公开(公告)日：2015-05-19

申请号：US13401634

申请日：2012-02-21

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC: H01L29/68 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, and a first conductive layer. The first stacked structure is formed on the substrate and includes a conductive structure and an insulating structure, and the conductive structure is disposed adjacent to the insulating structure. The first conductive layer is formed on the substrate and surrounds two side walls and a part of the top portion of the first stacked structure for exposing a portion of the first stacked structure.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括基板，第一堆叠结构和第一导电层。 第一堆叠结构形成在基板上，并且包括导电结构和绝缘结构，并且导电结构邻近于绝缘结构设置。 第一导电层形成在基板上并且包围第一层叠结构的两个侧壁和顶部的一部分，用于暴露第一堆叠结构的一部分。

公开(公告)号：US08922020B2

公开(公告)日：2014-12-30

申请号：US12983832

申请日：2011-01-03

Applicant: Shih-Hung Chen ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L23/48 ,  H01L27/115 ,  H01L21/033 ,  H01L23/528

CPC classification number: H01L27/11573 ,  H01L21/0337 ,  H01L21/0338 ,  H01L23/528 ,  H01L27/11565 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: An integrated circuit pattern comprises a set of lines of material having X and Y direction portions. The X and Y direction portions have first and second pitches, the second pitch being larger, such as at least 3 times larger, than the first pitch. The X direction portions are parallel and the Y direction portions are parallel. The end regions of the Y direction portions comprise main line portions and offset portions. The offset portions comprise offset elements spaced apart from and electrically connected to the main line portions. The offset portions define contact areas for subsequent pattern transferring procedures. A multiple patterning method, for use during integrated circuit processing procedures, provides contact areas for subsequent pattern transferring procedures.

Abstract translation: 集成电路图案包括具有X和Y方向部分的一组材料线。 X和Y方向部分具有第一和第二间距，第二间距比第一间距大至少3倍。 X方向部分是平行的，并且Y方向部分是平行的。 Y方向部分的端部区域包括主线部分和偏移部分。 偏移部分包括与主线部分间隔开并电连接到主线部分的偏移元件。 偏移部分限定用于后续图案转印过程的接触区域。 为了在集成电路处理过程中使用的多重图形化方法提供用于随后的图案转印过程的接触区域。

公开(公告)号：US08811077B2

公开(公告)日：2014-08-19

申请号：US13239760

申请日：2011-09-22

Applicant: Chun-Hsiung Hung ,  Hang-Ting Lue ,  Shih-Hung Chen

Inventor： Chun-Hsiung Hung ,  Hang-Ting Lue ,  Shih-Hung Chen

IPC: G11C5/06 ,  G11C16/04 ,  G11C5/02 ,  G11C7/18

CPC classification number: G11C5/06 ,  G11C7/18 ,  G11C13/0002 ,  G11C16/0483 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/1021 ,  H01L27/11206 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/792

Abstract: A 3D integrated circuit memory array has a plurality of plane positions. Multiple bit line structures have a multiple sequences of multiple plane positions. Each sequence characterizes an order in which a bit line structure couples the plane positions to bit lines. Each bit line is coupled to at least two different plane positions to access memory cells at two or more different plane positions.

Abstract translation: 3D集成电路存储器阵列具有多个平面位置。 多个位线结构具有多个平面位置的多个序列。 每个序列表征位线结构将平面位置耦合到位线的顺序。 每个位线耦合到至少两个不同的平面位置以访问两个或更多个不同平面位置处的存储器单元。

公开(公告)号：US08704205B2

公开(公告)日：2014-04-22

申请号：US13594353

申请日：2012-08-24

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

IPC: H01L47/00

CPC classification number: H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575

Abstract: A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

Abstract translation: 具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。 第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。 导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。 第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。 第一组晶体管结构在第一体积区域周围具有第一栅极。 第一导线连接到第一栅极以控制施加到第一栅极的电压。

公开(公告)号：US08692379B2

公开(公告)日：2014-04-08

申请号：US13594372

申请日：2012-08-24

Applicant: Shih-Hung Chen

Inventor： Shih-Hung Chen

IPC: H01L23/50

CPC classification number: H01L23/522 ,  H01L21/76816 ,  H01L21/76888 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A connector access region of an integrated circuit device includes a set of parallel conductors, extending in a first direction, and interlayer connectors. The conductors comprise a set of electrically conductive contact areas on different conductors which define a contact plane with the conductors extending below the contact plane. A set of the contact areas define a line at an oblique angle, such as less than 45° or 5° to 27°, to the first direction. The interlayer connectors are in electrical contact with the contact areas and extend above the contact plane. At least some of the interlayer connectors overlie but are electrically isolated from the electrical conductors adjacent to the contact areas with which the interlayer connectors are in electrical contact. The set of parallel conductors may include a set of electrically conductive layers with the contact plane being generally perpendicular to the electrically conductive layers.

Abstract translation: 集成电路器件的连接器接入区域包括沿第一方向延伸的一组平行导体和层间连接器。 导体包括在不同导体上的一组导电接触区域，其限定了在接触平面下方延伸的导体的接触平面。 一组接触区域以相对于第一方向的倾斜角度（例如小于45°或5°至27°）限定一条线。 层间连接器与接触区域电接触并在接触面上方延伸。 层间连接器中的至少一些覆盖在电绝缘体上，并与电接触部分相邻的电导体隔离。 该组平行导体可以包括一组导电层，其中接触平面大致垂直于导电层。

公开(公告)号：US20140021628A1

公开(公告)日：2014-01-23

申请号：US13607555

申请日：2012-09-07

Applicant: Yen-Hao Shih ,  Shih-Hung Chen ,  Teng-Hao Yeh ,  Chih-Wei Hu ,  Feng-Nien Tsai ,  Lo-Yueh Lin

Inventor： Yen-Hao Shih ,  Shih-Hung Chen ,  Teng-Hao Yeh ,  Chih-Wei Hu ,  Feng-Nien Tsai ,  Lo-Yueh Lin

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/53271 ,  H01L23/5329 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N−1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W−1 contact openings to create extended contact openings extending to W−1 conductive layers; 2n−1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.

Abstract translation: 一种使用IC器件的方法包括一叠介电/导电层，以形成从器件表面延伸到导电层的层间连接器。 通过电介质层产生接触开口到第一导电层。 N型蚀刻掩模，其中2N-1小于W，2N大于或等于W，其间具有间隔开的开放蚀刻区域和掩模区域。 层叠层仅通过W-1接触开口蚀刻以产生延伸到W-1导电层的延伸的接触开口; 对于每个蚀刻掩模n = 1,2，2n-1个导电层被蚀刻用于多达一半的接触开口。 。 。 用蚀刻掩模的开放蚀刻区域的不同组合蚀刻接触开口。 中间层连接器形成在接触开口中。

公开(公告)号：US08633099B1

公开(公告)日：2014-01-21

申请号：US13607555

申请日：2012-09-07

Applicant: Yen-Hao Shih ,  Shih-Hung Chen ,  Teng-Hao Yeh ,  Chih-Wei Hu ,  Feng-Nien Tsai ,  Lo-Yueh Lin

Inventor： Yen-Hao Shih ,  Shih-Hung Chen ,  Teng-Hao Yeh ,  Chih-Wei Hu ,  Feng-Nien Tsai ,  Lo-Yueh Lin

IPC: H01L21/44 ,  H01L21/4763 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/53271 ,  H01L23/5329 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N−1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W−1 contact openings to create extended contact openings extending to W−1 conductive layers; 2n−1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.

Abstract translation: 一种使用IC器件的方法包括一叠介电/导电层，以形成从器件表面延伸到导电层的层间连接。 通过电介质层产生接触开口到第一导电层。 N型蚀刻掩模，其中2N-1小于W，2N大于或等于W，其间具有间隔开的开放蚀刻区域和掩模区域。 层叠层仅通过W-1接触开口蚀刻以产生延伸到W-1导电层的延伸的接触开口; 对于每个蚀刻掩模n = 1,2，2n-1个导电层被蚀刻用于多达一半的接触开口。 。 。 用蚀刻掩模的开放蚀刻区域的不同组合蚀刻接触开口。 中间层连接器形成在接触开口中。

公开(公告)号：US08598032B2

公开(公告)日：2013-12-03

申请号：US13049303

申请日：2011-03-16

Applicant: Shih-Hung Chen ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L23/538 ,  H01L21/308

CPC classification number: H01L21/67069 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76838 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional stacked IC device has a stack of contact levels at an interconnect region. According to some examples of the present invention, it only requires a set of N etch masks to create up to and including 2N levels of interconnect contact regions at the stack of contact levels. According to some examples, 2x−1 contact levels are etched for each mask sequence number x, x being a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N. Methods create the interconnect contact regions aligned with landing areas at the contact levels.

Abstract translation: 三维堆叠IC器件在互连区域具有一层接触电平。 根据本发明的一些示例，其仅需要一组N个蚀刻掩模以在接触电平的叠层处产生多达且包括2N级的互连接触区域。 根据一些示例，对于每个掩码序列号x蚀刻2x-1接触电平，x是掩模的序列号，使得对于一个掩模x = 1，对于另一个掩模x = 2，依此类推，x = N 。 方法创建互连接触区域与接触层面上的着陆区域对齐。