公开(公告)号：US20160217849A1

公开(公告)日：2016-07-28

申请号：US15002302

申请日：2016-01-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Xian Liu ,  Vipin Tiwari ,  Hieu Van Tran

IPC: G11C11/419 ,  G11C16/14 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788

CPC classification number: G11C11/419 ,  G11C16/0458 ,  G11C16/14 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.

Abstract translation: 一种形成存储器件的方法，包括在衬底上形成第一绝缘层，第一导电层，第二绝缘层，第二导电层，第三绝缘层。 第一沟槽通过第三绝缘层，第二导电层，第二绝缘层和第一导电层形成，从而使第一导电层的侧面部分露出。 第一绝缘层形成在沿第一导电层的暴露部分延伸的第一沟槽的底部。 第一个沟槽填充有导电材料。 第二沟槽通过第三绝缘层，第二导电层，第二绝缘层和第一导电层形成。 在第二沟槽下的衬底中形成漏区。 导致一对存储单元，其中单个连续沟道区域在用于该对存储单元的漏极区域之间延伸。

公开(公告)号：US12205655B2

公开(公告)日：2025-01-21

申请号：US17841411

申请日：2022-06-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Nha Nguyen ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G06F3/06 ,  G06N3/063 ,  G06N3/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/10

Abstract: In one example, a method of testing a plurality of non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, comprises asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, all bit lines in the array; performing a deep programming operation on the array of non-volatile memory cells; and measuring a total current received from the bit lines.

公开(公告)号：US12061976B2

公开(公告)日：2024-08-13

申请号：US17181656

申请日：2021-02-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten ,  Nhan Do

IPC: G06N3/065 ,  G06F3/06 ,  G06F17/16 ,  G06N3/08 ,  G11C27/02

CPC classification number: G06N3/065 ,  G06F3/0688 ,  G06F17/16 ,  G06N3/08 ,  G11C27/02

Abstract: Numerous output circuits are disclosed for an analog neural memory system for a deep learning neural network. In one embodiment, an adaptable neuron circuit receives output current from a neuron and converts it into a voltage. In another embodiment, a current sample and hold circuit samples an input current and generates an output current. In another embodiment, a voltage sample and hold circuit samples an input voltage and generates an output voltage.

公开(公告)号：US12057170B2

公开(公告)日：2024-08-06

申请号：US18139908

申请日：2023-04-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Stephen Trinh ,  Thuan Vu ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/10 ,  G06N3/065 ,  G11C11/56 ,  G11C16/04 ,  G11C16/14 ,  G11C16/34

CPC classification number: G11C16/10 ,  G06N3/065 ,  G11C11/5628 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/3459

Abstract: In one example, a system comprises a neural network array of non-volatile memory cells arranged in rows and columns; and a logical cell comprising a first plurality of non-volatile memory cells in a first row of the array and a second plurality of non-volatile memory cells in a second row adjacent to the first row; wherein the first plurality of non-volatile memory cells and the second plurality of non-volatile memory cells are configured as one or more coarse cells and one or more fine cells.

公开(公告)号：US12033692B2

公开(公告)日：2024-07-09

申请号：US18124334

申请日：2023-03-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C11/54 ,  G06N3/045 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L29/423 ,  H01L29/788 ,  H10B41/30

CPC classification number: G11C11/54 ,  G06N3/045 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7883 ,  H10B41/30

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.

公开(公告)号：US11908513B2

公开(公告)日：2024-02-20

申请号：US18103383

申请日：2023-01-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari

IPC: G11C11/54 ,  G11C16/04 ,  G06N3/063 ,  G11C16/26 ,  G11C16/28 ,  H03F3/00 ,  H03M1/16 ,  G06N3/065 ,  H03M1/38

CPC classification number: G11C11/54 ,  G06N3/063 ,  G06N3/065 ,  G11C16/0416 ,  G11C16/0425 ,  G11C16/26 ,  G11C16/28 ,  H03F3/005 ,  H03M1/164 ,  H03M1/38

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, a system comprises a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W− values, and wherein one of the columns in the second array is a dummy column; wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)−(W−).

公开(公告)号：US11853856B2

公开(公告)日：2023-12-26

申请号：US16746852

申请日：2020-01-18

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh Bayat ,  Xinjie Guo ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten

IPC: G11C16/04 ,  G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/34 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/06

CPC classification number: G06N3/04 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06N3/045 ,  G06N3/063 ,  G11C11/54 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3436 ,  G11C29/38

Abstract: An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs. Various algorithms for tuning the memory cells to contain the correct weight values are disclosed.

公开(公告)号：US11847557B2

公开(公告)日：2023-12-19

申请号：US17885437

申请日：2022-08-10

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C11/56 ,  G06N3/065 ,  G06F3/06 ,  G06F17/16 ,  G06N3/08 ,  G11C13/00 ,  G11C16/04 ,  G11C16/28 ,  G06N3/048

CPC classification number: G06N3/065 ,  G06F3/061 ,  G06F3/0688 ,  G06F17/16 ,  G06N3/048 ,  G06N3/08 ,  G11C11/5642 ,  G11C13/004 ,  G11C16/0425 ,  G11C16/28 ,  G11C2211/563 ,  G11C2213/15

Abstract: Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. In one embodiment, a method comprises receiving an input voltage, multiplying the input voltage by a coefficient to generate an output voltage, applying the output voltage to a gate of a selected memory cell, performing a sense operating using the selected memory cell and a reference device to determine a value stored in the selected memory cell, wherein a slope of a current-voltage characteristic curve of the reference device and a slope of the current-voltage characteristic curve of the selected memory cell are approximately equal during the sense operation.

公开(公告)号：US11829859B2

公开(公告)日：2023-11-28

申请号：US17233006

申请日：2021-04-16

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh Bayat ,  Xinjie Guo ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten

IPC: G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/34 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/06

CPC classification number: G06N3/04 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06N3/045 ,  G06N3/063 ,  G11C11/54 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3436 ,  G11C29/38

Abstract: Numerous embodiments are disclosed for verifying a weight programmed into a selected non-volatile memory cell in a neural memory. In one embodiment, a circuit for verifying a weight programmed into a selected non-volatile memory cell in a neural memory comprises a converter for converting a target weight into a target current and a comparator for comparing the target current to an output current from the selected non-volatile memory cell during a verify operation. In another embodiment, a circuit for verifying a weight programmed into a selected non-volatile memory cell in a neural memory comprises a digital-to-analog converter for converting a target weight comprising digital bits into a target voltage, a current-to-voltage converter for converting an output current from the selected non-volatile memory cell during a verify operation into an output voltage, and a comparator for comparing the output voltage to the target voltage during a verify operation.

公开(公告)号：US20230368011A1

公开(公告)日：2023-11-16

申请号：US18227254

申请日：2023-07-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G06N3/065 ,  G06F17/16 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/14 ,  G06N3/044

CPC classification number: G06N3/065 ,  G06F17/16 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/3459 ,  G11C16/26 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/14 ,  G06N3/044 ,  G11C2216/04

Abstract: In one example, a method comprises performing a first programming process on a selected non-volatile memory cell, the first programming process comprising a plurality of program-verify cycles, wherein a programming voltage duration of increasing period is applied to one of a floating gate, a control gate terminal, an erase gate terminal, and a source line terminal of the selected non-volatile memory cell in each program-verify cycle after the first program-verify cycle.