公开(公告)号：US20090243116A1

公开(公告)日：2009-10-01

申请号：US12355112

申请日：2009-01-16

申请人： Frank Feustel ,  Thomas Werner ,  Michael Grillberger ,  Kai Frohberg

发明人： Frank Feustel ,  Thomas Werner ,  Michael Grillberger ,  Kai Frohberg

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76877 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： By forming a protection layer prior to the application of the planarization layer during a dual damascene strategy for first patterning vias and then trenches, enhanced etch fidelity may be accomplished. In other aspects disclosed herein, via openings and trenches may be patterned in separate steps, which may be accomplished by different etch behaviors of respective dielectric materials and/or the provision of an appropriate etch stop layer, while filling the via opening and the trench with a barrier material and a highly conductive metal may be achieved in a common fill sequence. Hence, the via opening may be formed on the basis of a reduced aspect ratio, while nevertheless providing a highly efficient overall process sequence.

摘要翻译： 通过在用于首先图形化通孔和沟槽的双镶嵌策略期间施加平坦化层之前形成保护层，可以实现增强的蚀刻保真度。 在本文公开的其他方面，通孔开口和沟槽可以在单独的步骤中被图案化，其可以通过各个介电材料的不同蚀刻行为和/或提供适当的蚀刻停止层来实现，同时将通孔开口和沟槽填充 可以在共同的填充序列中实现阻挡材料和高导电性金属。 因此，可以基于减小的纵横比来形成通孔开口，同时提供高效的总体工艺顺序。

公开(公告)号：US20080299733A1

公开(公告)日：2008-12-04

申请号：US11969412

申请日：2008-01-04

申请人： Patrick Press ,  Frank Wirbeleit ,  Joe Bloomquist ,  Kai Frohberg ,  Thomas Feudel

发明人： Patrick Press ,  Frank Wirbeleit ,  Joe Bloomquist ,  Kai Frohberg ,  Thomas Feudel

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature having a side surface and a top surface is formed over the substrate. A material layer is formed over the substrate. The material layer covers at least the side surface of the feature. An ion implantation process is performed to create an ion-implanted portion in the material layer. An etch process adapted to remove the ion-implanted portion at a greater etch rate than other portions of the material layer is performed.

摘要翻译： 形成半导体结构的方法包括提供半导体衬底。 具有侧表面和顶表面的特征形成在衬底上。 材料层形成在衬底上。 材料层至少覆盖该特征的侧表面。 进行离子注入工艺以在材料层中产生离子注入部分。 执行适于以比材料层的其它部分更高的蚀刻速率去除离子注入部分的蚀刻工艺。

公开(公告)号：US20080057705A1

公开(公告)日：2008-03-06

申请号：US11696226

申请日：2007-04-04

申请人： Frank Feustel ,  Kai Frohberg ,  Thomas Werner

发明人： Frank Feustel ,  Kai Frohberg ,  Thomas Werner

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/0273 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76823 ,  H01L21/76825

摘要： By forming a conductive material within an etch mask for an anisotropic etch process for patterning openings, such as vias, in a dielectric layer of a metallization structure, the probability for arcing events may be reduced, since excess charge may be laterally distributed. For example, an additional sacrificial conductive layer may be formed or an anti-reflecting coating (ARC) may be provided in the form of a conductive material in order to obtain the lateral charge distribution.

摘要翻译： 通过在蚀刻掩模内形成用于各向异性蚀刻工艺的导电材料，用于图案化金属化结构的电介质层中的诸如通路的开口，因为过量电荷可能横向分布，所以可以减小电弧事件的概率。 例如，可以形成附加的牺牲导电层，或者可以以导电材料的形式提供抗反射涂层（ARC），以获得横向电荷分布。

公开(公告)号：US20080026492A1

公开(公告)日：2008-01-31

申请号：US11695657

申请日：2007-04-03

申请人： Ralf Richter ,  Frank Feustel ,  Thomas Werner ,  Kai Frohberg

发明人： Ralf Richter ,  Frank Feustel ,  Thomas Werner ,  Kai Frohberg

IPC分类号： H01L21/469 ,  H01L21/66

CPC分类号： H01L21/02074 ,  H01L21/0209 ,  H01L21/02096

摘要： By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.

摘要翻译： 通过在中间制造阶段提供保护层，可以实现相对于颗粒污染和表面腐蚀的增加的表面保护。 在一些说明性实施例中，保护层可以在电测试过程中使用，其中相应的接触部分通过保护层接触，从而在相应的测量过程中显着地减少颗粒污染。

公开(公告)号：US07314793B2

公开(公告)日：2008-01-01

申请号：US11047129

申请日：2005-01-31

申请人： Kai Frohberg ,  Matthias Schaller ,  Massud Aminpur ,  Martin Mazur ,  Roberto Klingler

发明人： Kai Frohberg ,  Matthias Schaller ,  Massud Aminpur ,  Martin Mazur ,  Roberto Klingler

IPC分类号： H01L21/8238

CPC分类号： H01L29/6653 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/7843 ,  Y10S438/938

摘要： During the formation of a transistor element, sidewalls spacers are removed or at least partially etched back after ion implantation and silicidation, thereby rendering the mechanical coupling of a contact etch stop layer to the underlying drain and source regions more effective. Hence, the mechanical stress may be substantially induced by the contact etch step layer rather than by a combination of the spacer elements and the etch stop layer, thereby significantly facilitating the stress engineering in the channel region. By additionally performing a plasma treatment, different amounts of stress may be created in different transistor devices without unduly contributing to process complexity.

摘要翻译： 在形成晶体管元件期间，在离子注入和硅化之后去除侧壁间隔物或至少部分地回蚀，从而使接触蚀刻停止层与潜在的漏极和源极区域的机械耦合更有效。 因此，机械应力可以基本上由接触蚀刻步骤层引起，而不是间隔元件和蚀刻停止层的组合，从而显着地促进了沟道区域中的应力工程。 通过额外进行等离子体处理，可以在不同的晶体管器件中产生不同量的应力，而不会不利地导致工艺复杂性。

公开(公告)号：US20070077749A1

公开(公告)日：2007-04-05

申请号：US11423900

申请日：2006-06-13

申请人： Kai Frohberg ,  Katja Huy ,  Volker Kahlert

发明人： Kai Frohberg ,  Katja Huy ,  Volker Kahlert

IPC分类号： H01L21/4763

CPC分类号： C23C14/046 ,  H01L21/76843 ,  H01L21/76865

摘要： By performing a re-sputter process during the formation of a barrier layer for a contact opening in a tungsten-based process, the reliability of the tungsten deposition, as well as the performance of the resulting contact plug, may be enhanced. During the re-sputtering process, a thickness of the titanium-based barrier layer may be reduced at the contact bottom, while at the same time the material is re-condensed on critical lower sidewall portions of the contact opening.

摘要翻译： 通过在形成钨基工艺中的接触开口的阻挡层的过程中进行再溅射工艺，可以提高钨沉积的可靠性以及所得到的接触塞的性能。 在再溅射过程中，钛基阻挡层的厚度可以在接触底部减小，同时材料在接触开口的临界下侧壁部分上再凝结。

公开(公告)号：US20060113641A1

公开(公告)日：2006-06-01

申请号：US11177774

申请日：2005-07-08

申请人： Joerg Hohage ,  Hartmut Ruelke ,  Kai Frohberg

发明人： Joerg Hohage ,  Hartmut Ruelke ,  Kai Frohberg

IPC分类号： H01L23/58 ,  H01L21/302

CPC分类号： H01L29/7833 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/7843

摘要： A semiconductor structure comprises a transistor element formed in a substrate. A stressed layer is formed over the transistor element. The stressed layer has a predetermined compressive intrinsic stress having an absolute value of about 1 GPa or more. Due to this high intrinsic stress, the stressed layer exerts considerable elastic forces to the channel region of the transistor element. Thus, compressive stress is created in the channel region. The compressive stress leads to an increase of the mobility of holes in the channel region.

摘要翻译： 半导体结构包括形成在衬底中的晶体管元件。 应力层形成在晶体管元件上。 应力层具有绝对值为约1GPa以上的预定压缩本征应力。 由于这种高的固有应力，应力层对晶体管元件的沟道区域施加相当大的弹性力。 因此，在通道区域中产生压应力。 压缩应力导致通道区域中孔的迁移率的增加。

公开(公告)号：US20060094215A1

公开(公告)日：2006-05-04

申请号：US11145905

申请日：2005-06-06

申请人： Kai Frohberg ,  Matthias Schaller ,  Roberto Klingler

发明人： Kai Frohberg ,  Matthias Schaller ,  Roberto Klingler

IPC分类号： H01L21/4763

CPC分类号： H01L21/76837 ,  H01L21/31116 ,  H01L21/76834 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/1203

摘要： When forming line structures of semiconductor devices in accordance with the 90 nm technology, sidewall spacers of the lines are reduced in size immediately prior to the deposition of an etch stop layer that is formed on the device layer. Due to the reduced spacer elements or due to a complete removal of the spacer elements, the subsequent deposition of the etch stop layer and of the interlayer dielectric is significantly enhanced with respect to void formation and defect rate.

摘要翻译： 当根据90nm技术形成半导体器件的线结构时，在沉积形成在器件层上的蚀刻停止层之前，线的侧壁间隔物的尺寸被减小。 由于减少的间隔元件或由于间隔元件的完全去除，相对于空隙形成和缺陷率，蚀刻停止层和层间电介质的随后沉积显着增强。

公开(公告)号：US20060091471A1

公开(公告)日：2006-05-04

申请号：US11150635

申请日：2005-06-10

申请人： Kai Frohberg ,  Matthias Schaller ,  Joerg Hohage ,  Holger Schuehrer

发明人： Kai Frohberg ,  Matthias Schaller ,  Joerg Hohage ,  Holger Schuehrer

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L21/469

CPC分类号： H01L29/4933 ,  H01L21/31116 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/7843

摘要： A technique is provided that allows the formation of contact etch stop layers having different intrinsic stress for different transistors, while substantially avoiding any device degradation owing to the partial removal of the contact etch stop layer. Hereby, an additional thin etch stop layer is provided prior to the formation of the contact etch stop layers, thereby substantially maintaining the integrity of metal silicide regions, when a portion of an initially deposited contact etch stop layer is removed.

摘要翻译： 提供了允许形成对于不同晶体管具有不同固有应力的接触蚀刻停止层的技术，同时基本上避免了由于部分去除接触蚀刻停止层而导致的任何器件劣化。 因此，在形成接触蚀刻停止层之前，提供另外的薄蚀刻停止层，从而当初始沉积的接触蚀刻停止层的一部分被去除时，基本上保持金属硅化物区域的完整性。

公开(公告)号：US08492269B2

公开(公告)日：2013-07-23

申请号：US13234529

申请日：2011-09-16

申请人： Jens Heinrich ,  Ralf Richter ,  Torsten Huisinga ,  Kai Frohberg

发明人： Jens Heinrich ,  Ralf Richter ,  Torsten Huisinga ,  Kai Frohberg

IPC分类号： H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53257 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： In sophisticated semiconductor devices, superior contact resistivity may be accomplished for a given contact configuration by providing hybrid contact elements, at least a portion of which may be comprised of a highly conductive material, such as copper. To this end, a well-established contact material, such as tungsten, may be used as buffer material in order to preserve integrity of sensitive device areas upon depositing the highly conductive metal.

摘要翻译： 在复杂的半导体器件中，通过提供混合接触元件，对于给定的接触构型可以实现优异的接触电阻率，其中至少一部分可由高导电材料（例如铜）构成。 为此，可以使用诸如钨的良好接触材料作为缓冲材料，以便在沉积高导电性金属时保持敏感器件区域的完整性。