公开(公告)号：US20240389341A1

公开(公告)日：2024-11-21

申请号：US18776374

申请日：2024-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H10B51/30 ,  H01L21/28 ,  H01L23/522 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode arranged over a substrate. A gate dielectric layer is arranged over the gate electrode, and an active structure is arranged over the gate dielectric layer. A source contact and a drain contact are arranged over the active structure. The active structure includes a stack of cocktail layers alternating with first active layers. The cocktail layers include a mixture of a first material and a second material. The first active layers include a third material that is different than the first and second materials. The bottommost layer of the active structure is one of the cocktail layers.

公开(公告)号：US12150309B2

公开(公告)日：2024-11-19

申请号：US17591174

申请日：2022-02-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Song-Fu Liao ,  Hai-Ching Chen ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H10B51/30

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.

公开(公告)号：US20240379870A1

公开(公告)日：2024-11-14

申请号：US18316439

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wu-Wei Tsai ,  Hai-Ching Chen ,  Po-Ting Lin ,  Yan-Yi Chen ,  Yu-Ming Lin ,  Chung-Te Lin ,  Tzer-Min Shen ,  Yen-Tien Tung

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66

Abstract: The problem of providing transistors that can be manufactured to any specified threshold voltage withing a broad range of threshold voltages without creating leakage, capacitance, or process compatibility issues is solved by introducing a buried layer of a second dielectric composition into a gate dielectric of a first dielectric composition. The second dielectric composition is selected relative to the first dielectric composition so that dipoles form around the interface of the two dielectrics. The dipoles create an electric field that causes a shift in the threshold voltage. The buried layer has a higher dielectric constant than the gate dielectric, is thinner than the gate dielectric, and is proximate the channel.

公开(公告)号：US20240365558A1

公开(公告)日：2024-10-31

申请号：US18763112

申请日：2024-07-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H10B51/30 ,  H10B51/20 ,  H10B53/20 ,  H10B53/30

CPC classification number: H10B51/30 ,  H10B51/20 ,  H10B53/20 ,  H10B53/30

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a semiconductor layer overlying a substrate. A ferroelectric layer overlies the substrate. A pair of source/drain structures are disposed on the semiconductor layer. A lower metal layer is disposed along a lower surface of the ferroelectric layer. An upper metal layer is disposed along an upper surface of the ferroelectric layer.

公开(公告)号：US12127411B2

公开(公告)日：2024-10-22

申请号：US18363986

申请日：2023-08-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L29/40 ,  H01L21/28 ,  H01L23/522 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B51/30

CPC classification number: H10B51/30 ,  H01L23/5226 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode arranged over a substrate. A gate dielectric layer is arranged over the gate electrode, and an active structure is arranged over the gate dielectric layer. A source contact and a drain contact are arranged over the active structure. The active structure includes a stack of cocktail layers alternating with first active layers. The cocktail layers include a mixture of a first material and a second material. The first active layers include a third material that is different than the first and second materials. The bottommost layer of the active structure is one of the cocktail layers.

公开(公告)号：US12009301B2

公开(公告)日：2024-06-11

申请号：US17577805

申请日：2022-01-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5283 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226

Abstract: An interconnect structure is provided. The interconnect structure includes a first via in a first dielectric layer, a first metal line on and electrically connected to the first via, a first etching stop layer over the first dielectric layer, a second metal line over the first etching stop layer, and an encapsulating layer. The encapsulating layer includes a first vertical portion along a sidewall of the first metal line, a horizontal portion along an upper surface of the first etching stop layer, and a second vertical portion along a sidewall of the second metal line. The interconnect structure also includes a second dielectric layer nested within the encapsulating layer.

公开(公告)号：US20240088025A1

公开(公告)日：2024-03-14

申请号：US18519516

申请日：2023-11-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Yen Huang ,  Kai-Fang Cheng ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31111 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/5329 ,  H01L23/53295 ,  H01L21/76807 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

公开(公告)号：US20240064993A1

公开(公告)日：2024-02-22

申请号：US17885575

申请日：2022-08-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Song-Fu Liao ,  Kuo-Chang Chiang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L23/528 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/11597 ,  H01L23/5283 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

Abstract: A method of fabricating a transistor structure is provided. The method comprises forming a gate electrode in a dielectric layer of an interconnect structure; forming a monolayer on a portion of the dielectric layer laterally spaced from the gate electrode; sequentially forming a ferroelectric layer, a barrier layer and a channel layer on the gate electrode; and forming a source/drain electrode on the channel layer.

公开(公告)号：US11903217B2

公开(公告)日：2024-02-13

申请号：US17394757

申请日：2021-08-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H10B51/30 ,  H10B51/00 ,  H01L49/02

CPC classification number: H10B51/30 ,  H01L28/75 ,  H10B51/00 ,  H01L2924/1441

Abstract: An integrated chip including a semiconductor layer over a substrate. A pair of source/drains are arranged along the semiconductor layer. A first metal layer is over the substrate. A second metal layer is over the first metal layer. A ferroelectric layer is over the second metal layer. The first metal layer has a first crystal orientation and the second metal layer has a second crystal orientation different from the first crystal orientation.

公开(公告)号：US11901221B2

公开(公告)日：2024-02-13

申请号：US17829611

申请日：2022-06-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shao-Kuan Lee ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Cheng-Chin Lee

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L21/76829 ,  H01L21/7682 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/5329

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.