公开(公告)号：US09740255B2

公开(公告)日：2017-08-22

申请号：US15023066

申请日：2014-09-18

Applicant: TOHOKU UNIVERSITY

Inventor： Takashi Ohsawa ,  Tetsuo Endoh

IPC: G06F1/26 ,  G11C14/00 ,  G11C11/16

CPC classification number: G06F1/26 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697 ,  G11C14/0081

Abstract: A memory cell (101) is connected to a word line (WL), a bit line (BL), and a power supply line (PL), and includes a flip-flop storing data based on a change in resistance value of a magnetic tunnel junction element, and, a power gating field-effect transistor including a drain that is one end of a current path connected to the power supply line, and which has another end connected to the flip-flop. The ON and OFF states of the power gating field-effect transistor are controlled based on a control signal applied to a control terminal of the power gating field-effect transistor.

公开(公告)号：US09536584B2

公开(公告)日：2017-01-03

申请号：US14400950

申请日：2013-05-15

Applicant: NEC CORPORATION ,  TOHOKU UNIVERSITY

Inventor： Ryusuke Nebashi ,  Noboru Sakimura ,  Yukihide Tsuji ,  Ayuka Tada ,  Tadahiko Sugibayashi ,  Takahiro Hanyu ,  Tetsuo Endoh ,  Hideo Ohno

IPC: G11C11/00 ,  G11C11/16 ,  H03K19/18 ,  H03K3/356 ,  G11C13/00

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1673 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79 ,  H03K3/356121 ,  H03K19/18

Abstract: A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are connected, a reference resistive network as a reference resistance providing a tolerance of the memory structure to a resistance value of the resistive network of the memory structure, a writing part operable to selectively write or rewrite a value of each of the nonvolatile resistive elements in the resistive network into a maximum or a minimum corresponding to a logical value to be read when data are stored into the resistive network, and a logic circuit structure operable to use, as a logical value of the memory structure, a value obtained by comparison between the resistance value of the resistive network and the resistance value of the reference resistive network.

Abstract translation: 非易失性逻辑门装置被配置为包括其中连接有至少三个非易失性电阻元件的存储器结构的电阻网络，作为参考电阻的参考电阻网络，其提供存储器结构对电阻网络的电阻值的容限 所述写入部分可操作以选择性地将所述电阻网络中的每个所述非易失性电阻元件的值写入或重写为对应于当数据被存储到所述电阻网络中时要读取的逻辑值的最大值或最小值， 以及可操作地作为存储器结构的逻辑值使用通过比较电阻网络的电阻值和参考电阻网络的电阻值而获得的值的逻辑电路结构。

公开(公告)号：US20160372174A1

公开(公告)日：2016-12-22

申请号：US15101809

申请日：2014-12-03

Applicant: TOHOKU UNIVERSITY

Inventor： Takashi Ohsawa ,  Tetsuo Endoh

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/1697 ,  G11C14/0081

Abstract: A memory circuit (100) includes a plurality of memory cells (50), an N-type MOSFET (30a) and an N-type MOSFET (30b). The drain of the N-type MOSFET (30a) is connected to one of a pair of bit lines, and the drain of the N-type MOSFET (30b) is connected to the other of the pair of bit lines. The gate of the N-type MOSFET (30a) is connected to the drain of the N-type MOSFET (30b), and the gate of the N-type MOSFET (30b) is connected to the drain of the N-type MOSFET (30a).

Abstract translation: 存储电路（100）包括多个存储单元（50），N型MOSFET（30a）和N型MOSFET（30b）。 N型MOSFET（30a）的漏极连接到一对位线之一，并且N型MOSFET（30b）的漏极连接到该对位线中的另一条位线。 N型MOSFET（30a）的栅极连接到N型MOSFET（30b）的漏极，并且N型MOSFET（30b）的栅极连接到N型MOSFET的漏极（ 30a）。

公开(公告)号：US09318170B2

公开(公告)日：2016-04-19

申请号：US14758100

申请日：2013-12-25

Applicant: TOHOKU UNIVERSITY

Inventor： Takashi Ohsawa ,  Tetsuo Endoh

IPC: G11C11/00 ,  G11C7/22 ,  G11C13/00 ,  G11C11/16 ,  G11C14/00

CPC classification number: G11C7/22 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/0081 ,  G11C14/009

Abstract: A memory cell (1) includes a first storage circuit (2) with a write time t1 and a data retention time τ1 and a second storage circuit (3) with a write time t2 and a data retention time τ2 (t1

Abstract translation: 存储单元（1）包括具有写入时间t1和数据保持时间τ1的第一存储电路（2）和写入时间t2和数据保持时间τ2（t1

公开(公告)号：US09299714B2

公开(公告)日：2016-03-29

申请号：US14662194

申请日：2015-03-18

Applicant: SK hynix Inc. ,  Tohoku University

Inventor： Moon-Sik Seo ,  Tetsuo Endoh

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L27/11556 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7889

Abstract: A semiconductor device includes a channel layer protruding from a substrate and having protrusions extending from a sidewall thereof. Floating gates surrounding the channel layer are provided between the protrusions. Control gates surrounding the floating gates are stacked along the channel layer. Interlayer insulating layers are interposed between the control gates stacked along the channel layer. A level difference exists between a lateral surface of each of the floating gates, and a lateral surface of each of the protrusions.

公开(公告)号：US20240244983A1

公开(公告)日：2024-07-18

申请号：US18282277

申请日：2022-03-16

Applicant: TOHOKU UNIVERSITY

Inventor： Yoshiaki Saito ,  Shoji Ikeda ,  Tetsuo Endoh

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/85

CPC classification number: H10N50/10 ,  H10B61/00 ,  H10N50/85

Abstract: Provided are a magnetoresistive element in which the magnetization direction in a recording layer can be efficiently reversed with low resistance and without reducing reversal efficiency by a write current flowing in a heavy-metal layer; a magnetic memory; and an artificial intelligence system. A magnetoresistive element 10 includes: a heavy-metal layer 11 formed by stacking an Ir layer(s) 12 and a Pt layer(s) 13; a recording layer 16 provided to be opposed to the heavy-metal layer 11, and formed to include a first ferromagnetic layer having a reversible magnetization; a reference layer 18 formed to include a second ferromagnetic layer in which the magnetization direction is fixed; and a barrier layer 17 sandwiched between the first ferromagnetic layer and the second ferromagnetic layer, and formed of an insulator. The magnetization direction in the first ferromagnetic layer is reversed by a write current supplied to the heavy-metal layer 11.

公开(公告)号：US11862217B2

公开(公告)日：2024-01-02

申请号：US17430000

申请日：2020-02-15

Applicant: TOHOKU UNIVERSITY

Inventor： Masanori Natsui ,  Daisuke Suzuki ,  Akira Tamakoshi ,  Takahiro Hanyu ,  Tetsuo Endoh ,  Hideo Ohno

IPC: G11C11/16 ,  G06F17/14

CPC classification number: G11C11/1673 ,  G06F17/142 ,  G11C11/1653 ,  G11C11/1675 ,  G11C11/1697

Abstract: The present invention provides a device with low power and high performance, which can be applied to sensor nodes, a sensor node using the same, an access controller, a data transfer method, and execute a processing method in a microcontroller. The device has: an MRAM; a non-volatile CPU configured to include a nonvolatile memory; a non-volatile FPGA-ACC configured to include a nonvolatile memory and execute a part of operations on the nonvolatile CPU; and a power-gating control unit that controls power supply to each memory cell in the MRAM, the non-volatile CPU, and the non-volatile FPGA-ACC. The device is further provided with an access controller that controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

公开(公告)号：US11770981B2

公开(公告)日：2023-09-26

申请号：US17043404

申请日：2019-02-19

Applicant: TOHOKU UNIVERSITY

Inventor： Hiroaki Honjo ,  Tetsuo Endoh ,  Shoji Ikeda ,  Hideo Sato ,  Koichi Nishioka

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/85

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/85

Abstract: Provided are a magnetoresistance effect element and a magnetic memory having a shape magnetic anisotropy and using a recording layer having an anti-parallel coupling.
A first magnetic layer (3) and a second magnetic layer (5) of the magnetoresistance effect element include a ferromagnetic substance, have a magnetization direction variable to the direction perpendicular to a film surface and are magnetically coupled in an anti-parallel direction, and a junction size D (nm), which is a length of the longest straight line on an end face perpendicular to the thickness direction of the first magnetic layer (3) and the second magnetic layer (5), a film thickness t1 (nm) of the first magnetic layer (3), and a film thickness t2 (nm) of the second magnetic layer (5) satisfy relationships D

公开(公告)号：US11705176B2

公开(公告)日：2023-07-18

申请号：US17395210

申请日：2021-08-05

Applicant: TOHOKU UNIVERSITY

Inventor： Tetsuo Endoh ,  Hiroki Koike

IPC: G11C11/16 ,  G11C29/04

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C29/04

Abstract: A storage circuit includes: the array of a memory cell MC including a variable-resistance element; a conversion circuit that converts the resistance value of each memory cell into the signal level of an electric signal; a reference signal generation circuit that generates a reference signal common to a plurality of columns; a correction circuit that corrects one of the signal level of the reference signal and the signal level of the electric signal for each column of the array of the memory cell; and an RW circuit that determines data stored in the memory cell belonging to a corresponding column by comparing one of the reference level and the signal level of the electric signal, corrected by the correction circuit, and the other of the reference level and the signal level of the electric signal.

公开(公告)号：US11610083B2

公开(公告)日：2023-03-21

申请号：US16634512

申请日：2018-07-05

Applicant: TOHOKU UNIVERSITY

Inventor： Tetsuo Endoh ,  Hui Shen

IPC: G06K9/62 ,  G06N20/00 ,  G06F16/906

Abstract: Provided is a method for calculating an evaluation score of clustering quality, based on the number of clusters into which a plurality of data is clustered. The calculating the evaluation score includes: calculating a degree of internal compactness that is a sum of values, each being defined by normalizing a first index value by a first value that is based on a number of data within each cluster, the first index value indicating a degree of dispersion of data within each cluster; calculating a degree of external separation defined by normalizing a sum of a second index value for each cluster by a second value that is based on the number of clusters, the second index value indicating an index of a distance between the clusters; and calculating the evaluation score according to a predetermined formula having, as variables, the degree of internal compactness and the degree of external separation.