公开(公告)号：US10090249B2

公开(公告)日：2018-10-02

申请号：US15016144

申请日：2016-02-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/8238 ,  H01L23/535 ,  H01L29/08 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a first dielectric layer, a conductor, and a protection layer. The first gate structure is present on the substrate. The first spacer is present on a sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The first dielectric layer is present on the first gate structure and has an opening therein, in which the source drain structure is exposed through the opening. The conductor is electrically connected to the source drain structure, in which the conductor has an upper portion in the opening of the first dielectric layer and a lower portion between the upper portion and the source drain structure. The protection layer is present between the lower portion and the first spacer and between the upper portion and the source drain structure.

公开(公告)号：US10084085B2

公开(公告)日：2018-09-25

申请号：US14792303

申请日：2015-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/283 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a stop layer formed over a substrate and a fin structure formed over the stop layer. The FinFET device structure includes a gate structure formed over the fin structure and a source/drain (S/D) structure adjacent to the gate structure. A bottom surface of the S/D structure is located at a position that is higher than or level with a bottom surface of the stop layer.

公开(公告)号：US10032913B2

公开(公告)日：2018-07-24

申请号：US14990797

申请日：2016-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L21/768 ,  H01L21/308 ,  H01L23/535 ,  H01L29/417 ,  H01L29/66

Abstract: Contact structures, FinFET devices and methods of forming the same are disclosed. One of the contact structures includes a source/drain region, a mask layer, a connector and a shielding pattern. The source/drain region is between two gate stacks. A mask layer is over the gate stacks and has an opening corresponding to the source/drain region. The connector is electrically connected to the source/drain region, penetrates through the opening of the mask layer and protrudes above and below the mask layer. The shielding pattern is between the mask layer and the connector and in physical contact with the mask layer.

公开(公告)号：US09997520B2

公开(公告)日：2018-06-12

申请号：US14815419

申请日：2015-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Shin Cheng ,  Che-Cheng Chang

IPC: H01L29/00 ,  H01L27/108 ,  H01L49/02 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L27/10808 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/10855 ,  H01L28/86 ,  H01L28/87 ,  H01L28/91

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive structure in or over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the conductive structure. The semiconductor device structure includes a second dielectric layer over the first dielectric layer. The second dielectric layer has a second opening connected to the first opening and exposing the conductive structure. The semiconductor device structure includes a capacitor covering a first inner wall of the first opening, a second inner wall of the second opening, and a top surface of the conductive structure. The capacitor is electrically connected to the conductive structure.

公开(公告)号：US09991256B2

公开(公告)日：2018-06-05

申请号：US14968468

申请日：2015-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66545

Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy semiconductor fins on a substrate. The dummy semiconductor fins are adjacent to each other and are grouped into a plurality of fin groups. The dummy semiconductor fins of the fin groups are recessed one group at a time.

公开(公告)号：US09893060B2

公开(公告)日：2018-02-13

申请号：US14987294

申请日：2016-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/28114 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a core device, and an input/output (I/O) device. The core device is disposed on the substrate. The core device includes a first gate electrode having a bottom surface and at least one sidewall. The bottom surface of the first gate electrode and the sidewall of the first gate electrode intersect to form a first interior angle. The I/O device is disposed on the substrate. The I/O device includes a second gate electrode having a bottom surface and at least one sidewall. The bottom surface of the second gate electrode and the sidewall of the second gate electrode intersect to form a second interior angle greater than the first interior angle of the first gate electrode.

公开(公告)号：US09870955B2

公开(公告)日：2018-01-16

申请号：US15456735

申请日：2017-03-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Yi-Jen Chen ,  Yung-Jung Chang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/165

CPC classification number: H01L21/823814 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a semiconductor substrate and forming a dummy shielding layer over the semiconductor substrate and the gate stack. The method also includes forming source and drain features near the gate stack after the dummy shielding layer is formed. The method further includes removing the dummy shielding layer after the source and drain features are formed such that substantially no dummy shielding layer remains on the source and drain features.

公开(公告)号：US09812549B2

公开(公告)日：2017-11-07

申请号：US15257567

申请日：2016-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Chen-Hsiang Lu ,  Wei-Ting Chen ,  Yu-Cheng Liu

IPC: H01L21/3205 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/311 ,  H01L23/522 ,  H01L29/51

CPC classification number: H01L29/6653 ,  H01L21/28008 ,  H01L21/28247 ,  H01L21/31116 ,  H01L23/5226 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: One or more formation methods of a semiconductor device structure are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements. The method further includes partially removing the spacer elements such that an upper portion of the recess becomes wider. In addition, the method includes forming a metal gate stack in the recess and forming a protection element over the metal gate stack to fill the recess.

公开(公告)号：US20170316982A1

公开(公告)日：2017-11-02

申请号：US15646078

申请日：2017-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3083 ,  H01L21/311 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0657 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A substrate having a first area and a second area is provided. The substrate is patterned to form trenches in the substrate and semiconductor fins between the trenches, wherein the semiconductor fins comprises first semiconductor fins distributed in the first area and second semiconductor fins distributed in the second area. A first fin cut process is performed in the first area to remove portions of the first semiconductor fins. Insulators are formed in the trenches after the first fin cut process is performed. A second fin cut process is performed in the second area to remove portions of the second semiconductor fins until gaps are formed between the insulators in the second area. A gate stack is formed to partially cover the first semiconductor fins, the second semiconductor fins and the insulators.

公开(公告)号：US09793406B2

公开(公告)日：2017-10-17

申请号：US14925680

申请日：2015-10-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/06 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L29/7851 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-κ dielectric layer.