公开(公告)号：US07875516B2

公开(公告)日：2011-01-25

申请号：US11855695

申请日：2007-09-14

申请人： Roman Knoefler ,  Michael Specht ,  Josef Willer

发明人： Roman Knoefler ,  Michael Specht ,  Josef Willer

IPC分类号： H01L21/8234

CPC分类号： H01L27/11568 ,  H01L21/823828 ,  H01L27/105 ,  H01L27/11573

摘要： An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface of a semiconductor substrate, and a second gate stack including a memory layer stack on a second surface section. A first pattern is transferred into the first gate stack and a second pattern into the second gate stack.

摘要翻译： 公开了一种包括第一栅极堆叠和第二栅极堆叠的集成电路及其制造方法。 一个实施例提供包括在半导体衬底的主表面的第一表面部分上的第一栅极堆叠和栅极电介质的非易失性存储器单元，以及包括在第二表面部分上的存储层堆叠的第二栅极堆叠。 将第一图案转移到第一栅极堆叠中，将第二图案转移到第二栅极堆叠中。

公开(公告)号：US07868415B2

公开(公告)日：2011-01-11

申请号：US12177930

申请日：2008-07-23

申请人： Josef Willer ,  Michael Specht ,  Christoph Friederich ,  Doris Keitel-Schulz

发明人： Josef Willer ,  Michael Specht ,  Christoph Friederich ,  Doris Keitel-Schulz

IPC分类号： H01L23/58

CPC分类号： H01L21/28273 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

摘要： An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree.

摘要翻译： 描述了集成电路。 集成电路可以具有：由具有与半导体衬底的上表面平行的第一纵向方向的半导体衬底的材料形成的有源区线; 其中所述有源面积线具有至少一个形状支撑元件，所述支撑元件在平行于所述半导体衬底的上表面的第二纵向方向上延伸; 并且其中所述第二纵向方向相对于所述第一纵向方向以不等于0度并且不等于180度的角度布置。

公开(公告)号：US07790516B2

公开(公告)日：2010-09-07

申请号：US11483968

申请日：2006-07-10

申请人： Josef Willer ,  Nicolas Nagel

发明人： Josef Willer ,  Nicolas Nagel

IPC分类号： H01L21/82

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/792

摘要： A method of manufacturing at least one NAND-coupled semiconductor component is disclosed. A layer structure is formed on or above a semiconductor substrate. The layer structure is patterned to expose at least one region to be doped. The exposed region is doped and annealed. The patterned layer structure is at least partially removed. Replacing material is formed in the region in which the patterned layer structure has been removed, thereby forming the at least one NAND-coupled semiconductor component.

摘要翻译： 公开了制造至少一个NAND耦合的半导体部件的方法。 在半导体衬底上或上方形成层结构。 图案化层结构以暴露待掺杂的至少一个区域。 曝光区域被掺杂并退火。 图案化层结构至少部分地被去除。 在去除图案层结构的区域中形成更换材料，从而形成至少一个NAND耦合的半导体部件。

公开(公告)号：US07778073B2

公开(公告)日：2010-08-17

申请号：US11872655

申请日：2007-10-15

申请人： Josef Willer ,  Franz Hofmann ,  Detlev Richter ,  Nicolas Nagel

发明人： Josef Willer ,  Franz Hofmann ,  Detlev Richter ,  Nicolas Nagel

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11565 ,  H01L27/11568

摘要： Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.

摘要翻译： 本发明的实施例一般涉及用于制造集成电路的集成电路和方法。 在本发明的实施例中，提供了具有存储单元的集成电路。 存储单元可以包括载体中的沟槽，沟槽中的电荷俘获层结构，电荷俘获层结构包括至少两个分离的电荷俘获区，至少部分填充在沟槽中的导电材料以及源/漏区 旁边的沟槽。

公开(公告)号：US07741630B2

公开(公告)日：2010-06-22

申请号：US12028513

申请日：2008-02-08

申请人： Klaus-Dieter Ufert ,  Josef Willer

发明人： Klaus-Dieter Ufert ,  Josef Willer

IPC分类号： H01L47/00

CPC分类号： H01L27/101 ,  H01L27/222 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/149 ,  H01L45/1625 ,  H01L45/1675

摘要： An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the resistive memory element.

摘要翻译： 描述了包括存储单元的集成电路和集成电路的制造方法。 存储单元包括掩埋栅极选择晶体管和耦合到掩埋栅选择晶体管的电阻存储元件。 电阻性存储元件基于电阻式存储元件的电阻率存储信息。

公开(公告)号：US20080099834A1

公开(公告)日：2008-05-01

申请号：US11589303

申请日：2006-10-30

申请人： Josef Willer

发明人： Josef Willer

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/7851 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7854 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inverter which is at least partially formed in a semiconductor substrate includes a first transistor with a first channel and a second transistor with a second channel, wherein each of the first and second transistors is formed as a FinFET with ridge shaped channels. The first and second gate electrodes of the first and second transistors are adjacent to the first and second channels on at least three sides of the corresponding channel. The first gate electrode extends from a top surface of the first channel ridge to a first ridge depth along the first channel, and the second gate electrode extends from a top surface of the second channel ridge to a second ridge depth along the second channel, wherein the first ridge depth is greater than the second ridge depth.

摘要翻译： 至少部分地形成在半导体衬底中的反相器包括具有第一通道的第一晶体管和具有第二通道的第二晶体管，其中第一和第二晶体管中的每一个形成为具有脊形沟道的FinFET。 第一和第二晶体管的第一和第二栅电极在相应通道的至少三侧上与第一和第二通道相邻。 第一栅电极从第一通道脊的顶表面沿第一通道延伸到第一脊深度，并且第二栅极从第二通道脊的顶表面延伸到沿第二通道的第二脊深度，其中 第一脊深度大于第二脊深度。

公开(公告)号：US20080029803A1

公开(公告)日：2008-02-07

申请号：US11497528

申请日：2006-08-02

申请人： Klaus Dieter Ufert ,  Josef Willer ,  David Abookasis

发明人： Klaus Dieter Ufert ,  Josef Willer ,  David Abookasis

IPC分类号： H01L29/788

CPC分类号： H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1226

摘要： The present invention relates to a reprogrammable non-volatile memory cell which comprises a selection transistor and a data storage element. The invention further relates to a method of fabricating such a memory cell, as well as to a memory cell array comprising a number of such memory cells.

摘要翻译： 本发明涉及一种可编程非易失性存储单元，其包括选择晶体管和数据存储元件。 本发明还涉及一种制造这种存储单元的方法，以及包括许多这种存储单元的存储单元阵列。

公开(公告)号：US20070257293A1

公开(公告)日：2007-11-08

申请号：US11429929

申请日：2006-05-08

申请人： Josef Willer

发明人： Josef Willer

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L29/42352 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117

摘要： The semiconductor memory device has a substrate with a main surface, on which parallel trenches are arranged. A memory layer is disposed at the sidewalls of the trenches, and gate electrodes are disposed in the trenches. Buried bitlines are formed as doped regions between neighboring trenches. The buried bitlines abut the sidewalls of the trenches and comprise upper surfaces, which are arranged at a specified distance from the bottom of the trenches. Source/drain regions are formed by sections of the buried bitlines.

摘要翻译： 半导体存储器件具有主表面的衬底，平行的沟槽布置在其上。 存储层设置在沟槽的侧壁处，栅电极设置在沟槽中。 埋置的位线形成为相邻沟槽之间的掺杂区域。 埋置的位线邻接沟槽的侧壁并且包括上表面，其布置在距离沟槽的底部指定的距离处。 源极/漏极区域由掩埋位线的部分形成。

公开(公告)号：US20070048993A1

公开(公告)日：2007-03-01

申请号：US11217122

申请日：2005-08-31

申请人： Josef Willer ,  Patrick Haibach ,  Christoph Kleint ,  Nicolas Nagel

发明人： Josef Willer ,  Patrick Haibach ,  Christoph Kleint ,  Nicolas Nagel

IPC分类号： H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L27/115 ,  H01L27/11568

摘要： A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The product also includes a plurality of filling structures. Each filling structure separates from one another two respective contact structures arranged between two respective wordlines. The two respective contact structures are arranged at a distance from one another in the first direction. In the preferred embodiment, the contact structures have a top side provided at a distance from the substrate surface and extends to the substrate surface. The contact structures at the substrate surface have a width along the first direction that is larger than a width of the top sides of the contact structures along the first direction.

摘要翻译： 半导体产品包括具有基板表面的基板。 多个字线被布置成彼此间隔一定距离并沿着第一方向延伸。 在字线之间提供多个导电接触结构。 该产品还包括多个填充结构。 每个填充结构彼此分开布置在两个相应字线之间的两个相应的接触结构。 两个相应的接触结构在第一方向上彼此间隔一定距离。 在优选实施例中，接触结构具有设置在离基板表面一定距离处并且延伸到基板表面的顶侧。 衬底表面处的接触结构具有沿着第一方向的宽度，该宽度大于沿着第一方向的接触结构的顶侧宽度。

公开(公告)号：US07119395B2

公开(公告)日：2006-10-10

申请号：US10916013

申请日：2004-08-11

申请人： Martin Gutsche ,  Josef Willer ,  Cay-Uwe Pinnow ,  Ralf Symanczyk

发明人： Martin Gutsche ,  Josef Willer ,  Cay-Uwe Pinnow ,  Ralf Symanczyk

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42332

摘要： The storage layer (6) is in each case present above a region in which the channel region (3) adjoins a source/drain region (2) and is in each case interrupted above an intervening middle part of the channel region (3). The storage layer (6) is formed by material of the gate dielectric (4) and contains silicon or germanium nanocrystals or nanodots introduced through ion implantation. The gate electrode (5) is widened at the flanks by electrically conductive spacers (7).

摘要翻译： 存储层（6）在每种情况下都存在于沟道区域（3）邻接源极/漏极区域（2）的区域上方，并且在每个情况下都被中断在沟道区域（3）的中间部分之上。 存储层（6）由栅极电介质（4）的材料形成，并且包含通过离子注入引入的硅或锗纳米晶体或纳米点。 栅电极（5）通过导电间隔物（7）在侧面加宽。