公开(公告)号：US20070278574A1

公开(公告)日：2007-12-06

申请号：US11443144

申请日：2006-05-30

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Jong-Jan Lee

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Jong-Jan Lee

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02538 ,  H01L21/7624

摘要： A method is provided for forming a compound semiconductor-on-silicon (Si) wafer with a thermally soft insulator. The method forms a Si substrate, with a thermally soft insulator layer overlying the Si substrate. A silicon oxide layer is formed immediately overlying the thermally soft insulator layer, a top Si layer overlies the silicon oxide, and a lattice mismatch buffer layer overlies the top Si layer. A compound semiconductor layer is formed overlying the lattice mismatch buffer layer. The thermally soft insulator has a liquid phase temperature lower than the liquid phase temperatures of Si and the compound semiconductor. For example, the thermally soft insulator may have a flow temperature in the range of about 500° C. to 900° C., where the flow temperature is greater than the solid phase temperature and less than the liquid phase temperature.

摘要翻译： 提供了一种用热软性绝缘体形成硅化合物半导体（Si）晶片的方法。 该方法形成Si衬底，具有覆盖Si衬底的热软绝缘层。 形成刚好覆盖在热软绝缘体层上的氧化硅层，顶部Si层覆盖在氧化硅上，并且晶格失配缓冲层覆盖在顶部Si层上。 形成覆盖晶格失配缓冲层的化合物半导体层。 该热软绝缘体的液相温度低于Si和化合物半导体的液相温度。 例如，热软绝缘体可以具有在约500℃至900℃的范围内的流动温度，其中流动温度大于固相温度并且小于液相温度。

公开(公告)号：US07303971B2

公开(公告)日：2007-12-04

申请号：US11184660

申请日：2005-07-18

申请人： Sheng Teng Hsu ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Tingkai Li

IPC分类号： H01L21/20

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over the memory resistor material. An MSM bottom electrode overlies the memory resistor top electrode, a semiconductor layer overlies the MSM bottom electrode, and an MSM top electrode overlies the semiconductor layer. The MSM bottom electrode can be a material such as Pt, Ir, Au, Ag, TiN, or Ti. The MSM top electrode can be a material such as Pt, Ir, Au, TiN, Ti, or Al. The semiconductor layer can be amorphous Si, ZnO2, or InO2.

摘要翻译： 提供金属/半导体/金属（MSM）二进制开关存储器件和制造工艺。 该器件包括存储器电阻器底部电极，存储器电阻器底部电极上方的存储器电阻器材料，以及存储器电阻器材料上的存储器电阻器顶部电极。 MSM底部电极覆盖存储电阻器顶部电极，半导体层覆盖在MSM底部电极上，并且MSM顶部电极覆盖半导体层。 MSM底部电极可以是诸如Pt，Ir，Au，Ag，TiN或Ti的材料。 MSM顶部电极可以是诸如Pt，Ir，Au，TiN，Ti或Al的材料。 半导体层可以是非晶Si，ZnO 2或InO 2。

公开(公告)号：US07297642B2

公开(公告)日：2007-11-20

申请号：US11334015

申请日：2006-01-18

申请人： Wei Gao ,  Tingkai Li ,  Robert A. Barrowcliff ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Wei Gao ,  Tingkai Li ,  Robert A. Barrowcliff ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L21/31

CPC分类号： H05B33/145 ,  H01L21/3115 ,  H01L31/03046 ,  Y02E10/544

摘要： A method is provided for forming a rare earth (RE) element-doped silicon (Si) oxide film with nanocrystalline (nc) Si particles. The method comprises: providing a first target of Si, embedded with a first rare earth element; providing a second target of Si; co-sputtering the first and second targets; forming a Si-rich Si oxide (SRSO) film on a substrate, doped with the first rare earth element; and, annealing the rare earth element-doped SRSO film. The first target is doped with a rare earth element such as erbium (Er), ytterbium (Yb), cerium (Ce), praseodymium (Pr), or terbium (Tb). The sputtering power is in the range of about 75 to 300 watts (W). Different sputtering powers are applied to the two targets. Also, deposition can be controlled by varying the effective areas of the two targets. For example, one of the targets can be partially covered.

摘要翻译： 提供了一种用于形成具有纳米晶体（nc）Si颗粒的稀土（RE）元素掺杂硅（Si）氧化物膜的方法。 该方法包括：提供嵌入有第一稀土元素的Si的第一靶; 提供Si的第二个目标; 共溅射第一和第二个目标; 在掺杂有第一稀土元素的衬底上形成富Si氧化硅（SRSO）膜; 并对稀土元素掺杂的SRSO膜退火。 第一靶用铒（Er），镱（Yb），铈（Ce），镨（Pr）或铽（Tb）等稀土元素掺杂。 溅射功率在约75至300瓦（W）的范围内。 不同的溅射功率被应用于两个目标。 此外，可以通过改变两个目标的有效面积来控制沉积。 例如，其中一个目标可以被部分覆盖。

公开(公告)号：US07256426B2

公开(公告)日：2007-08-14

申请号：US11039463

申请日：2005-01-19

申请人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L27/15 ,  H01L21/00

CPC分类号： C23C14/16 ,  C03C17/34 ,  C23C14/10 ,  C23C28/322 ,  C23C28/323 ,  C23C28/345 ,  C23C28/3455 ,  C23C28/42 ,  H01L21/02164 ,  H01L21/02266 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0259 ,  H01L21/02631 ,  H01L21/02667 ,  H01L21/31608 ,  H01L33/26

摘要： Provided are an electroluminescence (EL) device and corresponding method for forming a rare earth element-doped silicon (Si)/Si dioxide (SiO2) lattice structure. The method comprises: providing a substrate; DC sputtering a layer of amorphous Si overlying the substrate; DC sputtering a rare earth element; in response, doping the Si layer with the rare earth element; DC sputtering a layer of SiO2 overlying the rare earth-doped Si; forming a lattice structure; annealing; and, in response to the annealing, forming nanocrystals in the rare-earth doped Si having a grain size in the range of 1 to 5 nanometers (nm). In one aspect, the rare earth element and Si are co-DC sputtered. Typically, the steps of DC sputtering Si, DC sputtering the rare earth element, and DC sputtering the SiO2 are repeated 5 to 60 cycles, so that the lattice structure includes the plurality (5-60) of alternating SiO2 and rare earth element-doped Si layers.

摘要翻译： 提供了一种用于形成稀土元素掺杂硅（Si）/二氧化硅（SiO 2）晶格结构的电致发光（EL）器件和相应的方法。 该方法包括：提供衬底; DC溅射覆盖衬底的非晶硅层; 直流溅射稀土元素; 作为响应，用稀土元素掺杂Si层; DC溅射一层SiO 2，覆盖稀土掺杂的Si; 形成晶格结构; 退火; 并且响应于退火，在具有1至5纳米（nm）范围内的晶粒尺寸的稀土掺杂Si中形成纳米晶体。 一方面，稀土元素和Si共溅射。 通常，DC溅射Si，DC溅射稀土元素和DC溅射SiO 2的步骤重复5至60个循环，使得晶格结构包括多个（5-60）交替的SiO 2和稀土元素掺杂 Si层。

公开(公告)号：US07193280B2

公开(公告)日：2007-03-20

申请号：US11039543

申请日：2005-01-19

申请人： Tingkai Li ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Sheng Teng Hsu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00 ,  H01L29/788

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/28291 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78391

摘要： One-transistor ferroelectric memory devices using an indium oxide film (In2O3), an In2O3 film structure, and corresponding fabrication methods have been provided. The method for controlling resistivity in an In2O3 film comprises: depositing an In film using a PVD process, typically with a power in the range of 200 to 300 watts; forming a film including In overlying a substrate material; simultaneously (with the formation of the In-including film) heating the substrate material, typically the substrate is heated to a temperature in the range of 20 to 200 degrees C.; following the formation of the In-including film, post-annealing, typically in an O2 atmosphere; and, in response to the post-annealing: forming an In2O3 film; and, controlling the resistivity in the In2O3 film. For example, the resistivity can be controlled in the range of 260 to 800 ohm-cm.

摘要翻译： 使用氧化铟膜（In 2 O 3 O 3），In 2 N 3 O 3的<！ - SIPO - >单晶体铁电存储器件 >膜结构，并提供相应的制造方法。 用于控制In 2 N 3 O 3膜中的电阻率的方法包括：使用PVD工艺沉积In膜，通常具有200至300瓦特的功率; 形成包括在衬底材料中的膜; 同时（形成含In膜）加热衬底材料，通常将衬底加热至20至200℃的温度范围; 在形成含In膜之后，通常在O 2气氛中进行后退火; 并且响应于后退火：形成In 2 N 3 O 3膜; 并且控制In 2 N 3 O 3膜中的电阻率。 例如，电阻率可以控制在260至800欧姆 - 厘米的范围内。

公开(公告)号：US07153708B2

公开(公告)日：2006-12-26

申请号：US11249883

申请日：2005-10-12

申请人： Tingkai Li ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Sheng Teng Hsu

IPC分类号： H01L21/00

CPC分类号： H01L21/28273 ,  C23C16/0272 ,  C23C16/40 ,  C23C16/56 ,  H01L21/28194 ,  H01L21/28291 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517

摘要： A method of forming a ferroelectric thin film on a high-k layer includes preparing a silicon substrate; forming a high-k layer on the substrate; depositing a seed layer of ferroelectric material at a relatively high temperature on the high-k layer; depositing a top layer of ferroelectric material on the seed layer at a relatively low temperature; and annealing the substrate, the high-k layer and the ferroelectric layers to form a ferroelectric thin film.

公开(公告)号：US07112837B2

公开(公告)日：2006-09-26

申请号：US11262545

申请日：2005-10-28

申请人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

IPC分类号： H01L29/76

CPC分类号： H01L27/1159 ,  H01L21/84 ,  H01L27/11502 ,  H01L27/11585

摘要： An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.

摘要翻译： 一种MFIS存储器阵列，具有多个具有连接多个MFIS存储晶体管栅极的字线的MFIS存储晶体管，其中连接到公共字线的所有MFIS存储晶体管具有公共源，每个晶体管漏极用作位输出，以及 沿着字线的所有MFIS通道被P +区隔开，并且通过P +区进一步连接到SOI衬底上的P +衬底区域。 还提供了在SOI衬底上制造MFIS存储器阵列的方法; 执行一个或多个字线的块擦除的方法以及有选择地编程位的方法。

公开(公告)号：US07008833B2

公开(公告)日：2006-03-07

申请号：US10755419

申请日：2004-01-12

申请人： Tingkai Li ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Sheng Teng Hsu

IPC分类号： H01L21/336

CPC分类号： H01L21/28291 ,  H01L29/78391

摘要： The present invention discloses a novel ferroelectric transistor design using a resistive oxide film in place of the gate dielectric. By replacing the gate dielectric with a resistive oxide film, and by optimizing the value of the film resistance, the bottom gate of the ferroelectric layer is electrically connected to the silicon substrate, eliminating the trapped charge effect and resulting in the improvement of the memory retention characteristics. The resistive oxide film is preferably a doped conductive oxide in which a conductive oxide is doped with an impurity species. The doped conductive oxide is most preferred to be In2O3 with the dopant species being hafnium oxide, zirconium oxide, lanthanum oxide, or aluminum oxide.

摘要翻译： 本发明公开了一种使用电阻氧化膜代替栅极电介质的新型铁电晶体管设计。 通过用电阻氧化膜代替栅极电介质，并且通过优化膜电阻的值，铁电层的底栅电连接到硅衬底，消除了俘获的电荷效应并导致存储保持力的提高 特点 电阻氧化膜优选为其中掺杂有杂质物质的导电氧化物的掺杂导电氧化物。 掺杂的导电氧化物最优选为掺杂物质为氧化铪，氧化锆，氧化镧或氧化铝的In 2 N 3 O 3。

公开(公告)号：US06995025B2

公开(公告)日：2006-02-07

申请号：US10873326

申请日：2004-06-21

申请人： Sheng Teng Hsu ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Tingkai Li

IPC分类号： H01L21/00

CPC分类号： H01L29/78391

摘要： A method of fabricating and programming a ferroelectric memory transistor for asymmetrical programming includes fabricating a ferroelectric memory transistor having a metal oxide layer overlaying a gate region; and programming the ferroelectric memory transistor so that a low threshold voltage is about equal to the intrinsic threshold voltage of the ferrorelectric memory transistor.

摘要翻译： 制造和编程用于非对称编程的铁电存储晶体管的方法包括制造具有覆盖栅极区域的金属氧化物层的铁电存储晶体管; 并且对铁电存储晶体管进行编程，使得低阈值电压约等于铁电介质存储晶体管的固有阈值电压。

公开(公告)号：US06991942B1

公开(公告)日：2006-01-31

申请号：US10953912

申请日：2004-09-28

申请人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

IPC分类号： H01L21/00

CPC分类号： H01L27/1159 ,  H01L21/84 ,  H01L27/11502 ,  H01L27/11585

摘要： An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.

摘要翻译： 一种MFIS存储器阵列，具有多个具有连接多个MFIS存储晶体管栅极的字线的MFIS存储晶体管，其中连接到公共字线的所有MFIS存储晶体管具有公共源，每个晶体管漏极用作位输出，以及 沿着字线的所有MFIS通道被P +区隔开，并且通过P +区进一步连接到SOI衬底上的P +衬底区域。 还提供了在SOI衬底上制造MFIS存储器阵列的方法; 执行一个或多个字线的块擦除的方法以及有选择地编程位的方法。