公开(公告)号：US20050032252A1

公开(公告)日：2005-02-10

申请号：US10934046

申请日：2004-09-03

申请人： Ryuji Kohno ,  Hideo Miura ,  Masatoshi Kanamaru ,  Hiroya Shimizu ,  Hideyuki Aoki

发明人： Ryuji Kohno ,  Hideo Miura ,  Masatoshi Kanamaru ,  Hiroya Shimizu ,  Hideyuki Aoki

IPC分类号： G01R1/06 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66 ,  G01R31/02 ,  G01R31/26

CPC分类号： G01R1/07314

摘要： A method of manufacturing a semiconductor device has forming process for forming a semiconductor device on a major surface of a wafer, and testing process for testing defect of the semiconductor device formed on the wafer. The testing process includes a step bringing a testing apparatus into contact with test electrodes of the semiconductor device. The testing apparatus has a contactor including a plurality of probes that come into contact with the test electrodes of the semiconductor device to be tested, and secondary electrodes electrically connected to the probes and disposed on a surface opposite to the probes; a substrate on which electrodes electrically communicated to the contactor by a conducting device. The conducting device is so formed that stress applied to the conducting device in the state where the probes are in contact with the test electrodes is larger than stress applied to the conducting device in the state where the probes are not in contact with the test electrodes.

摘要翻译： 制造半导体器件的方法具有在晶片的主表面上形成半导体器件的形成工艺和用于测试形成在晶片上的半导体器件的缺陷的测试过程。 测试过程包括使测试设备与半导体器件的测试电极接触的步骤。 测试装置具有接触器，该接触器包括与待测半导体器件的测试电极接触的多个探针，以及与探针电连接并设置在与探针相对的表面上的二次电极; 电极通过导电装置与接触器电连通的基板。 导电装置形成为在探针与测试电极接触的状态下施加到导电装置的应力大于在探针不与测试电极接触的状态下施加到导电装置的应力。

公开(公告)号：US06803294B2

公开(公告)日：2004-10-12

申请号：US10413562

申请日：2003-04-15

申请人： Yasuhiko Kouno ,  Hideo Miura ,  Nobuyoshi Matsuura ,  Masaharu Kubo

发明人： Yasuhiko Kouno ,  Hideo Miura ,  Nobuyoshi Matsuura ,  Masaharu Kubo

IPC分类号： H01L2146

CPC分类号： H01L29/66333 ,  H01L21/304 ,  H01L21/78 ,  H01L24/05 ,  H01L24/45 ,  H01L29/7395 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Gate oxide films, gate electrodes, base regions and emitter regions, which constitute IGBTs, are formed on a semiconductor wafer. A silicon oxide film is formed on the gate electrodes. Further, an emitter electrode is formed thereabove, and a passivation film is formed over the emitter electrode. Thereafter, an internal area of a back surface of the semiconductor wafer is polished to form a protrusion at its outer peripheral portion. Afterwards, an impurity is injected from the back surface of the semiconductor wafer to form a collector region. After a collector electrode is further formed, the semiconductor wafer is mounted on a stage smaller than the internal area and subjected to dicing along scribe areas. Thus, the strength of the semiconductor wafer is held by the protrusion, and cracking or the like of the semiconductor wafer can be reduced owing to the execution of the dicing in the above-described manner.

摘要翻译： 构成IGBT的栅极氧化膜，栅极电极，基极区域和发射极区域形成在半导体晶片上。 在栅电极上形成氧化硅膜。 此外，在上方形成发射电极，在发射电极上形成钝化膜。 此后，对半导体晶片的背面的内部区域进行研磨，在其外周部形成突起。 之后，从半导体晶片的背面注入杂质，形成集电极区域。 在进一步形成集电极之后，将半导体晶片安装在小于内部区域的台上，并沿划线区进行切割。 因此，半导体晶片的强度由突起保持，并且由于以上述方式执行切割，可以减小半导体晶片的破裂等。

公开(公告)号：US06692686B1

公开(公告)日：2004-02-17

申请号：US09557572

申请日：2000-04-25

申请人： Toshiaki Gonda ,  Hideo Miura ,  Hiroshi Noma ,  Takashi Miyazaki

发明人： Toshiaki Gonda ,  Hideo Miura ,  Hiroshi Noma ,  Takashi Miyazaki

IPC分类号： B29C4904

CPC分类号： B29C49/32 ,  B29C49/04 ,  B29C49/16 ,  B29C49/2408 ,  B29C49/421 ,  B29C49/4236 ,  B29C49/66 ,  B29C49/72 ,  B29C2049/2412 ,  B29C2049/2449 ,  B29C2049/2456 ,  B29C2049/325 ,  B29C2049/5875 ,  B29C2049/6027 ,  B29C2049/6036 ,  B29C2049/6615

摘要： A blow molding method includes steps of moving a split mold to a parison receiving position where a parison is supplied and receiving a parison, closing the split mold, performing blow molding at a blow molding position, and opening the split mold at a product discharge position and thereby discharging a product. The method further includes steps of: sequentially reciprocating each split mold in trains of split molds provided opposed to each other across the parison receiving position to and from a position opposed to the parison receiving position; and sequentially reciprocating the split mold disposed at the position where the split mold is opposed to the parsion receiving position to and from the parison receiving position for performing blow molding. There is also provided a blow molding apparatus for carrying out this molding method.

摘要翻译： 吹塑成型方法包括以下步骤：将分型模移动到型坯接收位置，在型坯接收位置供给型坯，接收型坯，闭合分模，在吹塑成型位置进行吹塑成型，并在产品排出位置打开分模 从而排出产品。 该方法还包括以下步骤：顺序地将分开的模具中的每个分割模具往相互对置的分型模具的列中相对地穿过所述型坯接收位置并从与所述型坯接收位置相对的位置移动; 并且将配置在与模型接收位置相对的位置处的分割模具依次往往与用于进行吹塑成形的型坯接收位置往复运动。 还提供了一种用于实施该成型方法的吹塑装置。

公开(公告)号：US06566149B1

公开(公告)日：2003-05-20

申请号：US09787250

申请日：2001-03-16

申请人： Masatoshi Kanamaru ,  Atsushi Hosogane ,  Yoshihige Endou ,  Ryuji Kouno ,  Hideo Miura ,  Shinji Tanaka ,  Hiroyuki Ohta ,  Akihiko Ariga ,  Naoto Ban ,  Hideyuki Aoki

发明人： Masatoshi Kanamaru ,  Atsushi Hosogane ,  Yoshihige Endou ,  Ryuji Kouno ,  Hideo Miura ,  Shinji Tanaka ,  Hiroyuki Ohta ,  Akihiko Ariga ,  Naoto Ban ,  Hideyuki Aoki

IPC分类号： G01R3126

CPC分类号： G01R3/00

摘要： For an inspection tray, a silicon substrate including a beam or a diaphragm, a probe and wiring is used. To highly accurately position a chip to be inspected, a second substrate for alignment is disposed on the substrate. To position the probe having wiring disposed on the first substrate and the electrode pad of the chip to be inspected, a projection or a groove is formed in each of both substrates. Preferably, the projection or groove should be formed by silicon anisotorpic etching to have a (111) crystal surface. As another machining method, dry etching can be used for machining the positioning projection or groove. By using an inductively coupled plasma-reactive ion etching (ICP-RIE) device for the dry etching, a vertical column or groove can be easily machined.

摘要翻译： 对于检查托盘，使用包括梁或隔膜，探针和布线的硅基板。 为了高精度地定位待检查的芯片，在基板上设置用于对准的第二基板。 为了定位具有设置在第一基板上的布线的探针和要检查的芯片的电极焊盘，在两个基板中的每一个中形成突起或凹槽。 优选地，突起或凹槽应由硅各向异性蚀刻形成以具有（111）晶体表面。 作为另一种加工方法，可以使用干蚀刻来加工定位突起或凹槽。 通过使用用于干蚀刻的电感耦合等离子体反应离子蚀刻（ICP-RIE）装置，可以容易地加工垂直的柱或槽。

公开(公告)号：US06544884B2

公开(公告)日：2003-04-08

申请号：US10022525

申请日：2001-12-20

申请人： Hiroyuki Ohta ,  Hideo Miura ,  Kazushige Sato ,  Takeshi Kimura ,  Hiyoo Masuda

发明人： Hiroyuki Ohta ,  Hideo Miura ,  Kazushige Sato ,  Takeshi Kimura ,  Hiyoo Masuda

IPC分类号： H01L214763

CPC分类号： H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower metallization layer, and the thickness B of the lower metallization layer satisfy relations given by (0.605/R)0.5

公开(公告)号：US06489648B2

公开(公告)日：2002-12-03

申请号：US09944485

申请日：2001-08-30

申请人： Tomio Iwasaki ,  Hiroshi Moriya ,  Hideo Miura ,  Shuji Ikeda

发明人： Tomio Iwasaki ,  Hiroshi Moriya ,  Hideo Miura ,  Shuji Ikeda

IPC分类号： H01L27108

CPC分类号： H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10873 ,  H01L28/56 ,  H01L28/57 ,  H01L29/4975 ,  H01L29/513

摘要： A semiconductor device has a gate dielectric film formed of zirconium oxide or hafnium oxide as a chief material and a gate electrode film in contact with the gate dielectric film on one principal surface side of a silicon substrate. The gate dielectric film contains an addition element to prevent diffusion of oxygen.

公开(公告)号：US06468845B1

公开(公告)日：2002-10-22

申请号：US09536642

申请日：2000-03-28

申请人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

发明人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

IPC分类号： H01L2184

CPC分类号： H01L21/28097 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/32053 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/823437 ,  H01L23/485 ,  H01L23/53257 ,  H01L23/53271 ,  H01L28/40 ,  H01L29/4925 ,  H01L29/4975 ,  H01L2924/0002 ,  Y10T117/10 ,  Y10T117/1004 ,  H01L2924/00

摘要： In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.

摘要翻译： 例如，通过氧化硅膜5在半导体衬底4上的氧化硅膜5上形成电极2时，栅电极2被构成为多个多晶硅层6的层叠结构。栅极部分 通过制造具有沉积非晶层的工艺的薄膜的方法和使该非晶材料结晶（再结晶）的方法形成电极2。 在这种情况下，非晶层的沉积被分开多次进行，使得一次沉积的非晶层的厚度不大于根据根据下式确定的临界应力值规定的厚度 在每个非晶层的沉积过程完成之后，非晶材料结晶，重复沉积非晶层的过程和结晶非晶材料的过程，由此多晶层6的层压结构具有必要的 获得膜厚度。 利用上述结构，可以防止半导体器件的电特性的恶化和层之间的剥离等缺陷的发生，层中的裂纹等，并且可以获得 通过多晶材料的层叠，具有所需膜厚度的小晶粒尺寸的多晶层。

公开(公告)号：US06348396B1

公开(公告)日：2002-02-19

申请号：US09702786

申请日：2000-11-01

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： A semiconductor device having a SGI structure produced by selecting D, T and R values for satisfying the formula: D

摘要翻译： 具有SGI结构的半导体器件通过选择满足下式的D，T和R值产生：其中D是元件形成区域的宽度，T是以微米为单位的槽的热氧化量，R是 在槽的端部底部的曲率半径具有优异的性能，例如在硅衬底中的凹槽底部产生的应力减小，并且不产生异常结漏电流。

公开(公告)号：US06337517B1

公开(公告)日：2002-01-08

申请号：US09151590

申请日：1998-09-11

申请人： Hiroyuki Ohta ,  Hideo Miura ,  Kazushige Sato ,  Takeshi Kimura ,  Hiroo Masuda

发明人： Hiroyuki Ohta ,  Hideo Miura ,  Kazushige Sato ,  Takeshi Kimura ,  Hiroo Masuda

IPC分类号： H01L2348

CPC分类号： H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower metallization layer, and the thickness B of the lower metallization layer satisfy relations given by (0.605/R)0.5

摘要翻译： 能够高速运转或具有许多功能的半导体装置。 在该装置中，防止了埋入电极的分层，从而提供了高可靠性。 接触孔的深度A，下部金属化层的最小线宽R和下部金属化层的厚度B满足关系式

公开(公告)号：US6057241A

公开(公告)日：2000-05-02

申请号：US66757

申请日：1998-04-27

申请人： Yasushi Matsuda ,  Hideo Miura ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Suzuki ,  Hirofumi Shimizu ,  Yasuko Yoshida ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

发明人： Yasushi Matsuda ,  Hideo Miura ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Suzuki ,  Hirofumi Shimizu ,  Yasuko Yoshida ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC分类号： H01L21/76 ,  H01L21/477

CPC分类号： H01L21/477 ,  H01L21/76

摘要： A silicon oxide film 2 which is exposed from a side wall of a groove 4a is etched to displace the silicon oxide film 2 backward toward an active region. The displacement amount is set to be equal to or more than a film thickness (Tr) of a silicon oxide film 5 to be formed on an inner wall of the groove 4a in a later thermal oxidation step and equal to or less than twice the film thickness (Tr) thereof. A shoulder portion of the groove 4a can be rounded by a low-temperature heat treatment at 1000.degree. C. or less, by controlling a heat treatment period such that the film thickness (Tr) of the silicon oxide film 5 is more than the film thickness (Tp) of the silicon oxide film 2 and equal to or less than three times the film thickness (Tr) thereof (Tp

摘要翻译： 蚀刻从槽4a的侧壁露出的氧化硅膜2，使氧化硅膜2朝向有源区域反向移动。 位移量被设定为等于或大于在随后的热氧化步骤中形成在凹槽4a的内壁上的氧化硅膜5的膜厚度（Tr），并且等于或小于两倍的膜 厚度（Tr）。 通过控制热处理时间使得氧化硅膜5的膜厚（Tr）大于膜的厚度（Tr），可以通过在1000℃以下的低温热处理使槽4a的肩部成圆形 氧化硅膜2的厚度（Tp）等于或小于其厚度（Tr）的三倍（Tp