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164 条记录 (耗时 0.035 秒)

    Semiconductor device
    81.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US07079443B2

    公开(公告)日：2006-07-18

    申请号：US10631752

    申请日：2003-08-01

    申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

    发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

    IPC分类号： G11C8/08

    CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

    摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

    摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

    Semiconductor memory device
    82.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20060156192A1

    公开(公告)日：2006-07-13

    申请号：US11102715

    申请日：2005-04-11

    申请人： Toshikazu Nakamura ,  Akira Kikutake ,  Kuninori Kawabata ,  Yasuhiro Onishi ,  Satoshi Eto

    发明人： Toshikazu Nakamura ,  Akira Kikutake ,  Kuninori Kawabata ,  Yasuhiro Onishi ,  Satoshi Eto

    IPC分类号： G11C29/00

    CPC分类号： G11C29/42 ,  G11C11/41

    摘要： Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. 1, an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

    摘要翻译： 公开了一种半导体存储器件，其能够任意地设定检验动作时的误差修正量的上限。 半导体存储器件具有计数器，寄存器和比较电路。 计数器对错误更正次数进行计数。 当外部输入上限设定信号（在图1 所示的情况下为外部上限提取信号）时，该寄存器改变数量的上限 错误更正，更改上限。 比较电路将误差校正次数与改变的上限进行比较。

    Polymer resin film and its production
    83.
    发明授权
    Polymer resin film and its production 失效
    聚合物树脂薄膜及其生产

    公开(公告)号：US07060214B2

    公开(公告)日：2006-06-13

    申请号：US10303907

    申请日：2002-11-26

    申请人： Yukihiro Katai ,  Tadahiro Tsujimoto ,  Toshikazu Nakamura

    发明人： Yukihiro Katai ,  Tadahiro Tsujimoto ,  Toshikazu Nakamura

    IPC分类号： B29C41/24

    CPC分类号： C08J5/18 ,  Y10T428/10 ,  Y10T428/1036 ,  Y10T428/24355 ,  Y10T428/24479 ,  Y10T428/31855

    摘要： In the transparent film of optical application or the support for photographic material produced by a solution film forming method, the polymer resin film on which any coating unevenness does not occur even when a functional layer is coated on the film surface and the manufacturing method for the film are proposed.To be concrete, a polymer resin film produced by the solution film forming method characterized by that the pitch a [cm] of the periodic thickness unevenness of web longitudinal direction and a thickness unevenness factor d [%] satisfy formula (1) described below. d≦0.46 a3−0.91 a2+0.60 a+1.01  (1) (on the premise that 0.2

    摘要翻译： 在光学应用的透明膜或通过溶液膜形成方法生产的照相材料的支持物中，即使在膜表面上涂覆功能层也不会发生任何涂布不均匀的聚合物树脂膜，以及用于 提出了电影。 具体而言，通过溶液膜形成方法制造的聚合物树脂膜的特征在于，幅材长度方向的周期性厚度不均匀性和厚度不均匀因子d [％]的沥青a [cm]满足下述式（1）。 <？in-line-formula description =“In-line Formulas”end =“lead”？> d <= 0.46 A -0.91 a <2> +0.60 a + 1.01（1）<？in-line-formula description =“In-line Formulas”end =“tail”？>（在0.2

    Clock synchronized dynamic memory and clock synchronized integrated circuit
    84.
    发明授权
    Clock synchronized dynamic memory and clock synchronized integrated circuit 有权
    时钟同步动态存储器和时钟同步集成电路

    公开(公告)号：US06898683B2

    公开(公告)日：2005-05-24

    申请号：US09922742

    申请日：2001-08-07

    申请人： Toshikazu Nakamura

    发明人： Toshikazu Nakamura

    IPC分类号： G11C11/4093 ,  G06F13/16 ,  G06F13/00

    CPC分类号： G06F13/1689 ,  Y02D10/14

    摘要： A synchronous dynamic memory has a clock input buffer receiving an external clock and outputting an input external clock, a command input buffer receiving commands, an address input buffer receiving addresses, and a data input buffer receiving data. During normal operation mode, the clock input buffer supplies the clock to the command, address, and data input buffers. During data hold modes, such as power down mode, the clock input buffer supplies the clock to the command input buffer but not to the address and data input buffers.

    摘要翻译： 同步动态存储器具有接收外部时钟并输出输入外部时钟的时钟输入缓冲器，接收命令的命令输入缓冲器，接收地址的地址输入缓冲器和接收数据的数据输入缓冲器。 在正常工作模式下，时钟输入缓冲器将时钟提供给命令，地址和数据输入缓冲区。 在数据保持模式（例如掉电模式）期间，时钟输入缓冲器将时钟提供给命令输入缓冲器，但不提供给地址和数据输入缓冲器。

    Semiconductor memory device with efficient redundancy operation
    85.
    发明授权
    Semiconductor memory device with efficient redundancy operation 失效
    半导体存储器件具有高效的冗余操作

    公开(公告)号：US06400618B1

    公开(公告)日：2002-06-04

    申请号：US09722472

    申请日：2000-11-28

    申请人： Toshikazu Nakamura ,  Yoshinori Okajima ,  Hiroyuki Sugamoto

    发明人： Toshikazu Nakamura ,  Yoshinori Okajima ,  Hiroyuki Sugamoto

    IPC分类号： G11C700

    CPC分类号： G11C29/785 ,  G11C29/808 ,  G11C29/848

    摘要： A semiconductor memory device, comprising a fuse circuit which indicates a defective portion in a row direction, and also indicates the defective portion in a column direction, and a control circuit which switches data buses to avoid the defective portion indicated in the column direction by the fuse circuit when the defective portion indicated in the row direction by the fuse circuit corresponds to a row address that is input to the semiconductor memory device.

    摘要翻译： 一种半导体存储器件，包括指示行方向上的缺陷部分的熔丝电路，并且还指示列方向上的缺陷部分，以及控制电路，其切换数据总线以避免列方向上指示的缺陷部分 当由熔丝电路在行方向指示的缺陷部分对应于输入到半导体存储器件的行地址时的熔丝电路。

    Semiconductor integrated circuit
    87.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US06201378B1

    公开(公告)日：2001-03-13

    申请号：US09301203

    申请日：1999-04-28

    申请人： Satoshi Eto ,  Masato Matsumiya ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

    发明人： Satoshi Eto ,  Masato Matsumiya ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

    IPC分类号： G05F316

    CPC分类号： G11C11/4074 ,  G11C5/147 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4099

    摘要： A semiconductor integrated circuit producing a given output voltage includes first and second operational amplifiers, and first and second transistors. The first and second operational amplifiers detect a voltage difference between a voltage applied to an input terminal and at least one reference voltage. The first and second transistors are turned ON or turned OFF according to the levels of voltages output from the first and second operational amplifiers. The first operational amplifier receives the output voltage at the input terminal. When the level of the output voltage becomes lower than the reference voltage, the first operational amplifier allows the first transistor to operate so as to raise the output voltage. In contrast, the second operational amplifier receives the output voltage at the input terminal. When the level of the output voltage exceeds the reference voltage, the second operational amplifier allows the second transistor to operate so as to lower the output voltage.

    摘要翻译： 产生给定输出电压的半导体集成电路包括第一和第二运算放大器以及第一和第二晶体管。 第一和第二运算放大器检测施加到输入端的电压与至少一个参考电压之间的电压差。 根据从第一和第二运算放大器输出的电压的电平，第一和第二晶体管导通或截止。 第一个运算放大器在输入端接收输出电压。 当输出电压的电平变得低于参考电压时，第一运算放大器允许第一晶体管工作，以便提高输出电压。 相反，第二运算放大器在输入端接收输出电压。 当输出电压的电平超过参考电压时，第二运算放大器允许第二晶体管工作，以降低输出电压。

    Agent accelerating collagen decomposition
    90.
    发明授权
    Agent accelerating collagen decomposition 失效
    代谢加速胶原蛋白分解

    公开(公告)号：US5840311A

    公开(公告)日：1998-11-24

    申请号：US732332

    申请日：1996-12-11

    申请人： Toshikazu Nakamura ,  Akira Shiota ,  Nobuaki Fujise ,  Mitsuo Namiki

    发明人： Toshikazu Nakamura ,  Akira Shiota ,  Nobuaki Fujise ,  Mitsuo Namiki

    IPC分类号： A61K38/22 ,  A61K38/00 ,  A61P1/16 ,  A61P9/10 ,  A61P11/00 ,  A61P13/02 ,  A61P15/00 ,  A61P17/00 ,  A61P43/00 ,  C07K1/16 ,  C07K14/475 ,  C07K14/52 ,  A61K38/18

    CPC分类号： C07K14/4753 ,  A61K38/00

    摘要： The present invention relates to an agent accelerating collagen decomposition and a therapeutic agent for fibrosis disorder containing HGFs (Hepatocyte Growth Factors) as an active ingredient. The active ingredients HGFs accelerate the decomposition of collagen (increase of collagenase activity), and can effectively treat fibrosis disorder by the acceleration of collagen decomposition. Therefore, according to the present invention, the prevention and treatment of a disease due to reduced collagenase activity and fibrosis disorders characterized by excessive production of fibroblast-derived connective tissue matrix are possible.

    摘要翻译： PCT No.PCT / JP95 / 00822 Sec。 371日期1996年12月11日第 102（e）日期1996年12月11日PCT提交1995年4月25日PCT公布。 公开号WO95 / 29694 日期：1995年11月9日本发明涉及加速胶原分解的药剂和含有HGF（肝细胞生长因子）作为活性成分的纤维化病症治疗剂。 活性成分HGF加速胶原蛋白分解（胶原酶活性增加），可通过加速胶原蛋白分解，有效治疗纤维化疾病。 因此，根据本发明，预防和治疗由于胶原酶活性降低引起的疾病和以成纤维细胞衍生的结缔组织基质的过量产生为特征的纤维化病症是可能的。