公开(公告)号：US08565661B2

公开(公告)日：2013-10-22

申请号：US12585635

申请日：2009-09-21

申请人： Michiya Okamoto ,  Hiroyuki Nagashima ,  Fumihito Itoh ,  Hiroshi Ono ,  Ken Amemiya ,  Masahiko Shakuto ,  Toshio Koike ,  Yuji Arai ,  Kaoru Yoshino ,  Takuma Iwasaki

发明人： Michiya Okamoto ,  Hiroyuki Nagashima ,  Fumihito Itoh ,  Hiroshi Ono ,  Ken Amemiya ,  Masahiko Shakuto ,  Toshio Koike ,  Yuji Arai ,  Kaoru Yoshino ,  Takuma Iwasaki

IPC分类号： G03G21/00

CPC分类号： G03G21/0029

摘要： A cleaning device that can be incorporated in an image forming apparatus which includes an image carrier configured to form a toner image, and a cleaning device configured to clean residual toner on the surface of the image carrier. The cleaning device includes a cleaning blade having a blade member provided to contact the surface of the image carrier and a holder to hold the blade member. The cleaning device further includes a frame to hold the cleaning blade and a vibration suppression member provided across the cleaning blade and the frame to couple the cleaning blade and the frame together and suppress vibration.

摘要翻译： 可以并入图像形成装置中的清洁装置，该图像形成装置包括构造成形成调色剂图像的图像载体，以及清洁装置，其构造成清洁图像载体表面上的残留调色剂。 清洁装置包括具有设置成接触图像载体的表面的刀片构件和用于保持刀片构件的保持器的清洁刀片。 清洁装置还包括保持清洁刮板的框架和设置在清洁刮板和框架两侧的振动抑制构件，以将清洁刮板和框架联接在一起并抑制振动。

公开(公告)号：US08755233B2

公开(公告)日：2014-06-17

申请号：US13240014

申请日：2011-09-22

申请人： Hiroyuki Nagashima

发明人： Hiroyuki Nagashima

IPC分类号： G11C16/26 ,  G11C16/34 ,  G11C16/14 ,  G11C11/56

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/349 ,  G11C16/3495

摘要： According to one embodiment, there is provided memory system including a non-volatile memory device, a monitoring unit, and a changing unit. The non-volatile memory device stores data. The monitoring unit monitors a characteristic of the non-volatile memory device when writing and erasing processes are performed to write and erase the data to and from the non-volatile memory device. The changing unit changes at least one of a value of a writing start voltage and an increase width of a writing voltage in the writing process in accordance with the monitored characteristic so that a time for the writing process is substantially identical to a target value. The writing process is a process in which a writing operation and a verification operation are alternately repeated.

摘要翻译： 根据一个实施例，提供了包括非易失性存储器件，监视单元和改变单元的存储器系统。 非易失性存储器件存储数据。 当执行写入和擦除处理时，监视单元监视非易失性存储器件的特性，以向非易失性存储器件写入和擦除数据。 改变单元根据所监视的特性改变写入开始电压的值和写入电压的增加宽度中的至少一个，使得写入处理的时间与目标值基本相同。 写入处理是交替重复写入操作和验证操作的处理。

公开(公告)号：US08575590B2

公开(公告)日：2013-11-05

申请号：US13038771

申请日：2011-03-02

申请人： Koichi Muraoka ,  Hiroyuki Nagashima

发明人： Koichi Muraoka ,  Hiroyuki Nagashima

IPC分类号： H01L47/00 ,  H01L27/10 ,  H01L29/06

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/2418 ,  H01L27/2463

摘要： According to one embodiment, there is provided a nonvolatile semiconductor memory device including a first interconnection layer, memory cell modules each of which is formed by laminating a non-ohmic element layer with an MIM structure having an insulating film sandwiched between metal films and a variable resistance element layer, and a second interconnection layer formed on the memory cell modules, the insulating film of the non-ohmic element layer includes plural layers whose electron barriers and dielectric constants are different, or contains impurity atoms that form defect levels in the insulating film or contains semiconductor or metal dots. The nonvolatile semiconductor memory device using non-ohmic elements and variable resistance elements in which memory cells can be miniaturized and formed at low temperatures is realized by utilizing the above structures.

摘要翻译： 根据一个实施例，提供了一种非易失性半导体存储器件，其包括第一互连层，存储单元模块，每个存储单元模块通过层叠具有MIM结构的非欧姆元件层而形成，所述MIM结构具有夹在金属膜之间的绝缘膜和可变 电阻元件层和形成在存储单元模块上的第二互连层，非欧姆元件层的绝缘膜包括其电子势垒和介电常数不同的多个层，或包含在绝缘膜中形成缺陷水平的杂质原子 或包含半导体或金属点。 通过利用上述结构，实现了使用非欧姆元件和可变电阻元件的非易失性半导体存储器件，其中存储单元可以在低温下小型化并形成。

公开(公告)号：US08441040B2

公开(公告)日：2013-05-14

申请号：US12886090

申请日：2010-09-20

申请人： Yoichi Minemura ,  Hiroyuki Nagashima

发明人： Yoichi Minemura ,  Hiroyuki Nagashima

IPC分类号： H01L23/52

CPC分类号： H01L27/2481 ,  H01L27/0688 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147

摘要： A semiconductor memory device according to an embodiment includes: a cell array block having, above a semiconductor substrate, a plurality of first and second wirings intersecting with one another, and a plurality of memory cells, the first and second wirings being separately formed in a plurality of layers in a perpendicular direction to the semiconductor substrate; and a first via wiring, connecting the first wiring in an n1-th layer of the cell array block with the first wiring in an n2-th layer, the semiconductor substrate or another metal wiring, and extending in a laminating direction of the cell array block. The first via wiring has a cross section orthogonal to the laminating direction of the cell array block. The cross section has an elliptical shape and a longer diameter in a direction perpendicular to the first wiring direction.

摘要翻译： 根据实施例的半导体存储器件包括：单元阵列块，其在半导体衬底上方具有彼此相交的多个第一和第二布线，以及多个存储单元，所述第一和第二布线分别形成在 在与半导体衬底垂直的方向上的多个层; 以及第一通孔布线，将第一电极阵列块的第n1层中的第一布线与第n2层的第一布线，半导体基板或其他金属布线连接，并且在电池阵列的层叠方向上延伸 块。 第一通孔布线具有与单元阵列块的层叠方向正交的截面。 横截面在垂直于第一布线方向的方向上具有椭圆形状和较长直径。

公开(公告)号：US08222677B2

公开(公告)日：2012-07-17

申请号：US12399376

申请日：2009-03-06

申请人： Yasuyuki Baba ,  Hiroyuki Nagashima

发明人： Yasuyuki Baba ,  Hiroyuki Nagashima

IPC分类号： H01L29/00

CPC分类号： H01L27/2409 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C2213/31 ,  G11C2213/71 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

摘要： A semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of contact plugs extending in the stack direction of the cell array layers to connect between the first lines, between the second lines, between the first or second line and the semiconductor substrate, or between the first or second line and another metal line, in the cell array layers. The first or second line in a certain one of the cell array layers has a contact connector making contact with both sides of the contact plug.

摘要翻译： 半导体存储器件包括半导体衬底; 形成在所述半导体衬底上的单元阵列块，并且包括多个堆叠的单元阵列层，每个堆叠的单元阵列层包括多个第一线，与所述多条第一线交叉的多个第二线，以及连接在所述第一和第二线之间的第一和第二线的交点处的存储单元 线条 以及在单元阵列层的堆叠方向上延伸的多个接触插塞，以在第一线之间，第二线之间，第一线或第二线与半导体衬底之间，或第一线或第二线与另一金属线之间连接 ，在单元阵列层。 电池阵列层中某一个的第一或第二线具有与接触插塞的两侧接触的接触连接器。

公开(公告)号：US20120002475A1

公开(公告)日：2012-01-05

申请号：US13232163

申请日：2011-09-14

申请人： Koki UENO ,  Hiroyuki Nagashima

发明人： Koki UENO ,  Hiroyuki Nagashima

IPC分类号： G11C16/04

CPC分类号： G11C16/349 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C29/028 ,  G11C29/50 ,  G11C29/82 ,  G11C2029/5006 ,  G11C2211/565

摘要： A non-volatile semiconductor memory device includes a non-volatile memory having a plurality of blocks each including a plurality of memory cells, a bit line electrically connected to one end of a current path of the memory cell, a source line electrically connected to the other end of the current path of the memory cell, a word line electrically connected to the gate electrode, a sense amplifier circuit electrically connected to the bit line and configured to read data from the memory cell, a row decoder electrically connected to the word line and configured to apply a read voltage at which the memory cell is set to an ON state to the word line, and a controller configured to measure a cell current flowing through the memory cell in the ON state to judge whether the memory cell has been degraded.

摘要翻译： 非挥发性半导体存储器件包括具有多个块的非易失性存储器，每个块包括多个存储器单元，电连接到存储单元的电流路径的一端的位线，电连接到存储单元的源极线 存储单元的电流路径的另一端，电连接到栅电极的字线，电连接到位线并被配置为从存储单元读取数据的读出放大器电路，电连接到字线的行解码器 并且被配置为将存储单元设置为ON状态的读取电压施加到字线，以及控制器，被配置为测量在ON状态下流过存储单元的单元电流，以判断存储单元是否已经劣化 。

公开(公告)号：US20110242875A1

公开(公告)日：2011-10-06

申请号：US13058952

申请日：2009-06-24

申请人： Hiroyuki Nagashima ,  Hirofumi Inoue

发明人： Hiroyuki Nagashima ,  Hirofumi Inoue

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/31 ,  G11C2213/72

摘要： A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.

摘要翻译： 一种非易失性半导体存储器件，包括一个单元阵列，该单元阵列包括多个第一线，与该多条第一线相交的多个第二线，以及多个存储单元，被布置成矩阵并连接在两条线之间的第一和第二线的交点处 每个存储单元包含其中电阻被非易失性地存储为数据的电可擦除可编程可变电阻元件和非欧姆元件的串行电路; 以及多个访问电路，其操作以同时访问在单元阵列中彼此物理分离的存储单元。

公开(公告)号：US20100328988A1

公开(公告)日：2010-12-30

申请号：US12677017

申请日：2008-09-09

申请人： Hiroyuki Nagashima ,  Hirofumi Inoue ,  Haruki Toda

发明人： Hiroyuki Nagashima ,  Hirofumi Inoue ,  Haruki Toda

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator is operative to generate plural types of write pulses for varying the resistance of the variable resistor in three or more stages based on ternary or higher write data. A selection circuit is operative to select a write target memory cell from the memory cell array based on a write address and supply the write pulse generated from the pulse generator to the selected memory cell.

摘要翻译： 非易失性半导体存储器件包括以矩阵形式布置的电可擦除可编程非易失性存储单元的存储单元阵列，每个存储单元使用可变电阻器。 脉冲发生器用于产生多种类型的写入脉冲，用于基于三进制或更高写入数据在三个或更多个阶段中改变可变电阻器的电阻。 选择电路可操作以基于写地址从存储单元阵列中选择写入目标存储单元，并将从脉冲发生器产生的写入脉冲提供给所选存储单元。

公开(公告)号：US20100238727A1

公开(公告)日：2010-09-23

申请号：US12788614

申请日：2010-05-27

申请人： Norihiro FUJITA ,  Hiroyuki Nagashima ,  Hiroshi Nakamura

发明人： Norihiro FUJITA ,  Hiroyuki Nagashima ,  Hiroshi Nakamura

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory.

摘要翻译： 非易失性半导体存储器包括：第一半导体芯片，其上安装有第一存储器; 安装有第二存储器的第二半导体芯片; 其中，在作为复制目的地的第二存储器中，在启动将读取使能操作识别为可启用操作的命令之后执行读取使能操作，以及作为第一存储器的源的第一存储器的数据 复制，被复制到第二个内存。

公开(公告)号：US20100237320A1

公开(公告)日：2010-09-23

申请号：US12726635

申请日：2010-03-18

申请人： Hiroyuki Nagashima

发明人： Hiroyuki Nagashima

IPC分类号： H01L45/00 ,  H01L21/82

CPC分类号： H01L27/2481 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

摘要： A nonvolatile semiconductor memory device includes a memory cell array where a plurality of memory cell layers having a plurality of first and second wires which cross each other and a memory cell provided at each intersection of these first and second wires are laminated on top of each other, wherein the memory cells have a variable resistance element and a non-ohmic element laminated in the direction in which the memory cell layers are laminated and tapered in such a manner that the area in a cross section gradually becomes smaller from the bottom memory cell layer towards the top memory cell layer, and the variable resistance element and the non-ohmic element in the memory cells in a certain memory cell layer are laminated in the same order as the variable resistance element and the non-ohmic element of the memory cells in another memory cell layer.

摘要翻译： 非易失性半导体存储器件包括存储单元阵列，其中具有彼此交叉的多个第一和第二布线的多个存储单元层和设置在这些第一和第二布线的每个交点处的存储单元层叠在一起 其中，所述存储单元具有层叠在所述存储单元层的方向上的可变电阻元件和非欧姆元件，所述非欧姆元件以从所述底部存储单元层的横截面逐渐变小的方式被层叠并逐渐变细 朝向顶部存储单元层，并且在特定存储单元层中的存储单元中的可变电阻元件和非欧姆元件以与可变电阻元件和存储单元的非欧姆元件相同的顺序层叠 另一个存储单元层。