公开(公告)号：US11994810B2

公开(公告)日：2024-05-28

申请号：US16966874

申请日：2019-11-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Li Xiao ,  Jiao Zhao ,  Dongni Liu ,  Minghua Xuan ,  Haoliang Zheng ,  Liang Chen ,  Hao Chen ,  Zhenyu Zhang ,  Jing Liu ,  Qi Qi

IPC: G03F9/00 ,  G03F1/42

CPC classification number: G03F9/7084 ,  G03F1/42 ,  G03F9/7076

Abstract: An alignment mark includes a first alignment marker located on a first surface of a substrate and a second alignment marker located on a second surface of the substrate. The second alignment marker is arranged to be matched with the first alignment marker, and capable of representing a process variation between the second alignment marker and the first alignment marker.

公开(公告)号：US11901286B2

公开(公告)日：2024-02-13

申请号：US17334320

申请日：2021-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei Peng ,  Chih-Min Hsiao ,  Ching-Hsu Chang ,  Jiann-Tyng Tzeng

IPC: H01L23/00 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394 ,  G03F1/42 ,  H01L23/528 ,  G06F30/31 ,  H01L21/768

CPC classification number: H01L23/5226 ,  G03F1/42 ,  G06F30/392 ,  G06F30/394 ,  G06F30/31 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528

Abstract: A method of generating an integrated circuit (IC) layout diagram includes obtaining a grid of intersecting first and second pluralities of tracks corresponding to adjacent metal layers, determining that first and second pitches of the respective first and second pluralities of tracks conform to a first rule, applying a via positioning pattern to the grid whereby via regions are restricted to alternating diagonal grid lines, positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines, and generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.

公开(公告)号：US20240012340A1

公开(公告)日：2024-01-11

申请号：US18366097

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ching Lee ,  Te-Chih Huang ,  Yu-Piao Fang

IPC: G03F7/00 ,  G03F1/22 ,  G03F1/24 ,  G03F1/42 ,  H01L23/544

CPC classification number: G03F7/70633 ,  G03F1/22 ,  G03F1/24 ,  G03F1/42 ,  H01L23/544 ,  H01L2223/54426

Abstract: An overlay mark includes a first, a second, a third, and a fourth component. The first component is located in a first region of the first overlay mark and includes a plurality of gratings that extend in a first direction. The second component is located in a second region of the first overlay mark and includes a plurality of gratings that extend in the first direction. The third component is located in a third region of the first overlay mark and includes a plurality of gratings that extend in a second direction different from the first direction. The fourth component is located in a fourth region of the first overlay mark and includes a plurality of gratings that extend in the second direction. The first region is aligned with the second region. The third region is aligned with the fourth region.

公开(公告)号：US20230268285A1

公开(公告)日：2023-08-24

申请号：US18310743

申请日：2023-05-02

Applicant: Taiwan Semiconductor Manufacturing, Ltd.

Inventor： Chih-Chia Hu ,  Chang-Ching Yu ,  Ming-Fa Chen

IPC: H01L23/544 ,  H01L21/56 ,  G03F9/00 ,  G03F7/00 ,  G03F1/00 ,  G03F1/42

CPC classification number: H01L23/544 ,  G03F1/00 ,  G03F1/42 ,  G03F7/70475 ,  G03F7/70633 ,  G03F9/708 ,  H01L21/56 ,  H01L21/60 ,  H01L2223/54426

Abstract: A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.

公开(公告)号：US11676908B2

公开(公告)日：2023-06-13

申请号：US16716167

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chia Hu ,  Chang-Ching Yu ,  Ming-Fa Chen

IPC: H01L23/544 ,  H01L21/56 ,  G03F9/00 ,  G03F7/00 ,  G03F1/00 ,  G03F1/42 ,  H01L21/60

CPC classification number: H01L23/544 ,  G03F1/00 ,  G03F1/42 ,  G03F7/70475 ,  G03F7/70633 ,  G03F9/708 ,  H01L21/56 ,  H01L21/60 ,  H01L2223/54426

Abstract: A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.

公开(公告)号：US20190199972A1

公开(公告)日：2019-06-27

申请号：US16227207

申请日：2018-12-20

Applicant: CANON KABUSHIKI KAISHA

Inventor： Tadaki Miyazaki

IPC: H04N7/18 ,  H04N5/232 ,  G03F1/42 ,  G03F9/00

CPC classification number: H04N7/183 ,  G03F1/42 ,  G03F9/7088 ,  H04N5/232

Abstract: An alignment apparatus performs alignment of a substrate is provided. The apparatus comprises a stage that moves while holding a substrate, an imaging device that captures an image of a mark on the substrate, and a processor that obtains a position of the mark based on the image of the mark. The imaging device includes an image sensor and a storage device that stores image data obtained by the image sensor. The imaging device performs next image capturing after the image sensor performs accumulation of charge and transfer of image data to the storage device is completed. The apparatus moves the stage for next image capturing concurrently with transfer of the image data to the storage device when capturing an image of the mark using the imaging device at a plurality of positions while moving the stage.

公开(公告)号：US20190072848A1

公开(公告)日：2019-03-07

申请号：US16121354

申请日：2018-09-04

Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION ,  SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION

Inventor： Lingyi GUO ,  Yi Shih LIN

IPC: G03F1/36 ,  G03F1/42

CPC classification number: G03F1/36 ,  G03F1/42 ,  G03F7/70425 ,  G03F7/70633

Abstract: An overlay compensation method and a related system are presented. The method includes: acquiring a first offset vector reflecting the relative position between overlay marks of a middle and a bottom target layers; acquiring a second offset vector reflecting the relative position between the overlay marks of a top and the middle target layers; decomposing the first offset vector into a first compensable component and a first uncompensable component; decomposing the second offset vector into a second compensable component and a second uncompensable component; computing minimum values of the first uncompensable component and the second uncompensable component; computing optimized values for the first compensable component and the second compensable component; and computing a third compensable component of a third offset vector reflecting the relative position between the overlay marks of the top and the bottom target layers.

公开(公告)号：US20180348647A1

公开(公告)日：2018-12-06

申请号：US15778093

申请日：2016-11-03

Applicant: ASML NETHERLANDS B.V.

Inventor： Carolus Johannes Catharina SCHOORMANS ,  Petrus Franciscus VAN GILS ,  Johannes Jacobus Matheus BASELMANS

IPC: G03F7/20 ,  G03F9/00 ,  G03F1/42

CPC classification number: G03F7/70516 ,  G03F1/42 ,  G03F7/70725 ,  G03F7/70775 ,  G03F9/7019 ,  G03F9/7049 ,  G03F9/7088

Abstract: A measurement method comprising using multiple radiation poles to illuminate a diffraction grating on a mask at a mask side of a projection system of a lithographic apparatus, coupling at least two different resulting diffraction orders per illumination pole through the projection system, using the projection system to project the diffraction orders onto a grating on a wafer such that a pair of combination diffraction orders is formed by diffraction of the diffraction orders, coupling the combination diffraction orders back through the projection system to detectors configured to measure the intensity of the combination diffraction orders, and using the measured intensity of the combination diffraction orders to measure the position of the wafer grating.

公开(公告)号：US20180314150A1

公开(公告)日：2018-11-01

申请号：US15545390

申请日：2016-02-01

Applicant: ASML Netherlands B.V.

Inventor： Derk Servatius Gertruda BROUNS ,  Dennis DE GRAAF ,  Robertus Cornelis Martinus DE KRUIF ,  Paul JANSSEN ,  Matthias KRUIZINGA ,  Arnoud Willem NOTENBOOM ,  Daniel Andrew SMITH ,  Beatrijs Louise Marie-Joseph Katrien VERBRUGGE ,  James Norman WILEY

IPC: G03F1/84 ,  G03F1/22 ,  G03F1/64 ,  G03F1/66 ,  G03F1/42

CPC classification number: G03F1/84 ,  G03F1/22 ,  G03F1/42 ,  G03F1/62 ,  G03F1/64 ,  G03F1/66

Abstract: A method comprising the steps of receiving a mask assembly comprising a mask and a removable EUV transparent pellicle held by a pellicle frame, removing the pellicle frame and EUV transparent pellicle from the mask, using an inspection tool to inspect the mask pattern on the mask, and subsequently attaching to the mask an EUV transparent pellicle held by a pellicle frame. The method may also comprise the following steps: after removing the pellicle frame and EUV transparent pellicle from the mask, attaching to the mask an alternative pellicle frame holding an alternative pellicle formed from a material which is substantially transparent to an inspection beam of the inspection tool; and after using an inspection tool to inspect the mask pattern on the mask, removing the alternative pellicle held by the alternative pellicle frame from the mask in order to attach to the mask the EUV transparent pellicle held by the pellicle frame.

公开(公告)号：US20180180946A1

公开(公告)日：2018-06-28

申请号：US15324975

申请日：2016-11-24

Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd

Inventor： Li ZHAO ,  Bangyin Peng

IPC: G02F1/1337 ,  G02F1/13 ,  G02F1/1334 ,  G03F1/32 ,  G03F1/42

CPC classification number: G02F1/133788 ,  G02F1/1303 ,  G02F1/133351 ,  G02F1/1334 ,  G02F1/133753 ,  G02F2001/13345 ,  G02F2001/133757 ,  G03F1/32 ,  G03F1/42

Abstract: Disclosed is an apparatus for improving optical alignment of panels manufactured on a same mother substrate. The technical defect in the prior art which affects product quality can be eliminated. The apparatus for improving optical alignment of panels manufactured on a same mother substrate includes a mother substrate (1), N columns of chips in a first group (2), N columns of chips in a second group (3), and a photomask (4). The N columns of chips in the first group (2) and the N columns of chips in the second group (3) are arranged in an alternate manner and are arranged on the mother substrate (1). An area of the chips in the second group (3) is larger than an area of the chips in the first group (2). The photomask (4) covers the N columns of chips in the first group (2) and the N columns of chips in the second group (3) so that ultraviolet irradiates the N columns of chips in the first group (2) and the N columns of chips in the second group (3) after passing through the photomask (4). N is a positive integer. The apparatus can be used in manufacturing of TFT-LCD.