公开(公告)号：US20170310338A1

公开(公告)日：2017-10-26

申请号：US15513266

申请日：2015-09-17

申请人： NEC Corporation

发明人： Shinichi HORI

IPC分类号： H03M3/00 ,  H03F3/217 ,  H03M9/00 ,  H04L27/36

CPC分类号： H03M3/39 ,  H03F3/217 ,  H03F3/2175 ,  H03F3/24 ,  H03F2200/171 ,  H03F2200/331 ,  H03M3/456 ,  H03M3/47 ,  H03M9/00 ,  H04L27/36

摘要： This invention enables to efficiently improve the signal-to-noise power ratio of a delta-sigma modulator without increasing the operating frequency. A digital modulation device 40 includes: a setting unit 41 that sets mutually different default values for N delta-sigma modulation units 42-1 to 42-N; N delta-sigma modulation units 42-1 to 42-N that input signals for each clock cycle indicated in a first clock signal and then perform delta-sigma modulation on the input signals to output modulated signals including noise signals having values that change in accordance with default values; and a serial output unit 43 that inputs, in order, the modulated signals output by the delta-sigma modulation units 42-1 to 42-N for each clock cycle indicated in a second clock signal, the second clock signal having a clock cycle that is 1/N of the clock cycle of the first clock signal, and then serializes and outputs the modulated signals.

公开(公告)号：US20170085349A1

公开(公告)日：2017-03-23

申请号：US15165088

申请日：2016-05-26

申请人： MediaTek Inc.

发明人： Stacy Ho ,  Wei-Hsin Tseng

IPC分类号： H04L5/00 ,  H03M3/00 ,  H03M1/06 ,  H04B1/12 ,  H03M1/46

CPC分类号： H04L5/0041 ,  H03M1/0617 ,  H03M1/466 ,  H03M3/406 ,  H03M3/41 ,  H03M3/426 ,  H03M3/47 ,  H04B1/0075 ,  H04B1/123 ,  H04L5/001 ,  H04L27/2647

摘要： Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.

公开(公告)号：US09455737B1

公开(公告)日：2016-09-27

申请号：US15049933

申请日：2016-02-22

申请人： QUALCOMM Incorporated

发明人： Omid Rajaee ,  Changsok Han ,  Liang Dai ,  Seyed Arash Mirhaj ,  Ganesh Kiran

IPC分类号： H03M3/00

CPC分类号： H03M3/464 ,  H03M1/1023 ,  H03M1/46 ,  H03M3/37 ,  H03M3/422 ,  H03M3/47

摘要： Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alternately sample and process an input signal and provide a feedback signal for the DSM using excess loop delay (ELD). In other aspects, the DSM may be implemented using a two-step SAR quantizer. For example, a first SAR ADC may sample an input signal to generate a most-significant bit (MSB) portion of an output of the DSM, while the second SAR ADC may subsequently sample a residue from the first SAR ADC conversion and generate a least-significant bit (LSB) portion of the output of the DSM. With these techniques, higher bandwidths may be obtained in high accuracy delta-sigma ADCs without using increased sampling rates.

摘要翻译： 本公开的某些方面提供了使用时间交织（TI）逐次逼近寄存器（SAR）模数转换器（ADC）的Δ-Σ调制器（DSM）。 例如，两个SAR ADC可以配置为交替采样和处理输入信号，并使用多余的环路延迟（ELD）为DSM提供反馈信号。 在其他方面，DSM可以使用两步SAR量化器来实现。 例如，第一SAR ADC可以采样输入信号以产生DSM的输出的最高有效位（MSB）部分，而第二SAR ADC可以随后从第一SAR ADC转换中采样残留，并产生最少 - DSM的输出的高位（LSB）部分。 利用这些技术，可以在高精度Δ-ΣADC中获得更高的带宽，而不使用提高的采样率。

公开(公告)号：US20160020781A1

公开(公告)日：2016-01-21

申请号：US14745354

申请日：2015-06-19

申请人： HRI Laboratories, LLC

发明人： Cynthia D. Baringer ,  Zhiwei A. Xu ,  Peter Petre ,  Donald A. Hitko ,  Albert Cosand

IPC分类号： H03M3/00

CPC分类号： H03M3/47 ,  H03M1/066 ,  H03M3/358 ,  H03M3/37 ,  H03M3/454 ,  H03M3/46

摘要： A delta sigma modulator which has improved the dynamic range. The ΔΣ modulator has a plurality of ADCs and a plurality of DACs, the plurality of ADCs and DACs are connected in a loop. The plurality of ADCs are coupled with an incoming analog signal. A clock generator provides a plurality of clock signals which control the plurality of ADCs and the plurality of DACs, the clock signals being offset relative to each other in the time domain thereby enabling each ADC in the plurality of ADCs one at a time and each DAC in the plurality of DACs one at a time so that the ΔΣ modulator processes data in the incoming analog signal in an interleaved fashion. The delta sigma modulator has an Nth order filter in a forward path of the loop.

摘要翻译： 改进了动态范围的Δ-Σ调制器。 ＆Dgr＆＆ 调制器具有多个ADC和多个DAC，多个ADC和DAC以环路连接。 多个ADC与输入的模拟信号耦合。 时钟发生器提供控制多个ADC和多个DAC的多个时钟信号，时钟信号在时域中相对于彼此偏移，从而使得多个ADC中的每个ADC一次一个，并且每个DAC 在多个DAC中，一次一个，使得＆Dgr＆ 调制器以交错方式处理输入模拟信号中的数据。 ΔΣ调制器在环路的前向通路中具有N阶滤波器。

公开(公告)号：US08994571B1

公开(公告)日：2015-03-31

申请号：US13608832

申请日：2012-09-10

申请人： Hossein Zarei ,  Chieh-Yu Hsieh

发明人： Hossein Zarei ,  Chieh-Yu Hsieh

IPC分类号： H03M1/12

CPC分类号： H03M3/47 ,  H03M3/40

摘要： An analog-to-digital converter (ADC) and a receiver that includes the ADC is disclosed. The ADC includes a first filter configured to receive a signal in an I-signal path of the receiver and a second filter configured to receive a signal in a Q-signal path of the receiver. The ADC further includes a quantizer alternatingly in connection with the first and second filters, and at least one DAC alternatingly in connection with the first and second filters. Switches in the ADC are configured to alternate connection between an input of the quantizer and outputs of the first and second filters, and are also configured to alternate connection between an output of the at least one DAC and inputs of the first and second filters.

摘要翻译： 公开了一种模数转换器（ADC）和包括该ADC的接收器。 ADC包括被配置为接收接收机的I信号路径中的信号的第一滤波器和被配置为接收接收机的Q信号路径中的信号的第二滤波器。 ADC还包括与第一和第二滤波器交替地交替的量化器，以及与第一和第二滤波器交替地交替的至少一个DAC。 ADC中的开关被配置为在量化器的输入和第一和第二滤波器的输出之间交替连接，并且还被配置为在至少一个DAC的输出与第一和第二滤波器的输入之间交替连接。

公开(公告)号：US08264392B1

公开(公告)日：2012-09-11

申请号：US12963347

申请日：2010-12-08

申请人： Hossein Zarei ,  Chieh-Yu Hsieh

发明人： Hossein Zarei ,  Chieh-Yu Hsieh

IPC分类号： H03M1/12

CPC分类号： H03M3/47 ,  H03M3/40

摘要： An analog-to-digital converter (ADC) and a receiver that includes the ADC is disclosed. The ADC includes a first filter configured to receive a signal in an I-signal path of the receiver and a second filter configured to receive a signal in a Q-signal path of the receiver. The ADC further includes a quantizer alternatingly in connection with the first and second filters, and at least one DAC alternatingly in connection with the first and second filters. Switches in the ADC are configured to alternate connection between an input of the quantizer and outputs of the first and second filters, and are also configured to alternate connection between an output of the at least one DAC and inputs of the first and second filters.

摘要翻译： 公开了一种模数转换器（ADC）和包括该ADC的接收器。 ADC包括被配置为接收接收机的I信号路径中的信号的第一滤波器和被配置为接收接收机的Q信号路径中的信号的第二滤波器。 ADC还包括与第一和第二滤波器交替地交替的量化器，以及与第一和第二滤波器交替地交替的至少一个DAC。 ADC中的开关被配置为在量化器的输入和第一和第二滤波器的输出之间交替连接，并且还被配置为在至少一个DAC的输出与第一和第二滤波器的输入之间交替连接。

公开(公告)号：US20120063548A1

公开(公告)日：2012-03-15

申请号：US13230660

申请日：2011-09-12

申请人： Bradley John Morris ,  Arthur Thomas Gerald Fuller

发明人： Bradley John Morris ,  Arthur Thomas Gerald Fuller

IPC分类号： H04L27/00

CPC分类号： H04L27/22 ,  H03M3/462 ,  H03M3/47 ,  H03M7/3028 ,  H04B1/0007

摘要： A receiver and method is provided for sigma-delta converting an RF signal to a digital signal and downconverting to a digital baseband signal. The RF signal is split into N phases, as can be accomplished using a sample and hold circuit, and each phase is digitized, as can be accomplished using an analog-to-digital (A/D) sigma-delta converter. Polyphase decimation techniques and demodulation are applied to the phased signals to generate a demodulated digital signal. The demodulated digital signal is further downconverted to the appropriate baseband signal.

摘要翻译： 提供了一种接收机和方法，用于将RF信号转换成数字信号并下变频成数字基带信号。 RF信号被分为N个相位，可以使用采样和保持电路实现，并且每个相位被数字化，如可以使用模数（A / D）Σ-Δ转换器所实现的。 将多相抽取技术和解调应用于相控信号以产生解调数字信号。 解调的数字信号进一步下变频到适当的基带信号。

公开(公告)号：US20120001782A1

公开(公告)日：2012-01-05

申请号：US13256524

申请日：2011-01-07

申请人： Tadashi Morita

发明人： Tadashi Morita

IPC分类号： H03M3/02

CPC分类号： H03M3/47

摘要： A ΔΣADC is provided that is capable of suppressing increase of a circuit scale without losing noise shaping function even when a switching speed of a switch for performing time-division process is lower than a sampling rate of the ΔΣADC. For a code values provided by a comparator (105), the ΔΣADC (100) has a first storage section (106-1) and a second storage section (106-2) respectively for signal sequences (a first signal sequence and a second signal sequence) constituting a time-divisionally combined signal. Then, one of the two storage sections (i.e. the first storage section (106-1) and the second storage section (106-2)) that corresponds to a branch selection signal is configured to store the code value obtained from the comparator (105). On the other hand, one of the two storage sections (i.e. the first storage section (106-1) and the second storage section (106-2)) that is not the storage section corresponding to the branch selection signal is configured to hold the already stored code value.

摘要翻译： 提供了一种能够抑制电路规模增加而不失去噪声整形功能的ADC，即使用于执行时分处理的开关的开关速度低于＆Dgr＆amp; ADC的采样率 。 对于由比较器（105）提供的代码值，＆amp;＆amp; ADC（100）具有分别用于信号序列的第一存储部分（106-1）和第二存储部分（106-2）（第一信号序列 和第二信号序列）构成时分组合信号。 然后，对应于分支选择信号的两个存储部分（即，第一存储部分（106-1）和第二存储部分（106-2））之一被配置为存储从比较器（105）获得的代码值 ）。 另一方面，不是与分支选择信号对应的存储部的两个存储部（即，第一存储部（106-1）和第二存储部106-2）中的一个被配置为保持 已经存储的代码值。

公开(公告)号：US07916054B2

公开(公告)日：2011-03-29

申请号：US12436778

申请日：2009-05-07

申请人： R. Jacob Baker

发明人： R. Jacob Baker

IPC分类号： H03M3/00

CPC分类号： H03M3/47

摘要： A K-Delta-1-Sigma modulator filters or integrates (Sigma) the difference (Delta) between K-feedback paths and an input signal. By using K-feedback paths the topology enables sample rates that are K times the clock frequency of any one feedback path. The sigma block can be implemented in a number of ways including an active or passive integrator or a filter with specific characteristics. When implemented as an integrator, the sigma block is common to all the feedback paths, so that the modulation noise is pushed to a portion of the spectrum where it can be reduced by filtering. The delta block can be implemented in a number of ways including analog adders or switched capacitors.

摘要翻译： K-Delta-1-Sigma调制器将K反馈路径和输入信号之间的差值（Delta）滤波或积分（Sigma）。 通过使用K反馈路径，拓扑使得采样速率是任何一个反馈路径的时钟频率的K倍。 西格玛块可以以多种方式实现，包括有源或无源积分器或具有特定特征的滤波器。 当实现为积分器时，西格玛块对于所有反馈路径是公共的，使得调制噪声被推送到频谱的一部分，其中可以通过滤波来减少调制噪声。 Δ块可以通过多种方式实现，包括模拟加法器或开关电容器。

公开(公告)号：US07880653B2

公开(公告)日：2011-02-01

申请号：US12363201

申请日：2009-01-30

申请人： Merit Y. Hong ,  Mohammad Nizam U. Kabir

发明人： Merit Y. Hong ,  Mohammad Nizam U. Kabir

IPC分类号： H03M3/00

CPC分类号： H03M3/464 ,  H03M3/35 ,  H03M3/43 ,  H03M3/47

摘要： Embodiments include integrator systems, switched-capacitor circuits, and methods of their operation. An integrator system comprises a differential amplifier and first and second sampling modules. The first sampling module includes a first capacitor and a first set of switches. The first set of switches changes a connection status between the first capacitor and first and second amplifier input terminals when a change in a polarity of a differential input signal does not occur between consecutive switching cycles, and refrains from changing the connection status when the change in the polarity does occur. The second sampling module includes a second capacitor and a second set of switches. The second set of switches changes a connection status between the second capacitor and the first and second amplifier input terminals when the change in the polarity does occur, and refrains from changing the connection status when the change in the polarity does not occur.

摘要翻译： 实施例包括积分器系统，开关电容器电路及其操作方法。 积分器系统包括差分放大器和第一和第二采样模块。 第一采样模块包括第一电容器和第一组开关。 当在连续的开关周期之间不发生差分输入信号的极性的变化时，第一组开关改变第一电容器与第一和第二放大器输入端子之间的连接状态，并且当改变连接状态时不改变连接状态 极性确实发生。 第二采样模块包括第二电容器和第二组开关。 当发生极性变化时，第二组开关改变第二电容器与第一和第二放大器输入端子之间的连接状态，并且当不发生极性变化时，不改变连接状态。