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公开(公告)号：US09520285B2
公开(公告)日：2016-12-13
申请号：US14350916
申请日：2012-10-23
发明人： Peter Ward
IPC分类号： H01L29/15 , H01L21/02 , H01L29/66 , H01L29/739 , H01L29/04 , H01L29/16 , H01L29/74 , H01L21/308
CPC分类号： H01L21/02529 , H01L21/02381 , H01L21/02447 , H01L21/0262 , H01L21/02642 , H01L21/02645 , H01L21/3081 , H01L29/045 , H01L29/1608 , H01L29/66068 , H01L29/66363 , H01L29/7393 , H01L29/7395 , H01L29/74
摘要： A method comprises providing a monocrystalline silicon wafer (11) having a principal surface (17) which supports a masking layer (24), for example silicon dioxide or polycrystalline silicon, having windows (25) to expose corresponding regions of the silicon wafer, forming silicon carbide seed regions (30) on the exposed regions of the wafer, for example by forming carbon and converting the carbon into silicon carbide, and growing monocrystalline silicon carbide (31) on the silicon carbide seed regions. Thus, monocrystalline silicon carbide can be formed selectively on the silicon wafer which can help to avoid wafer bow.
摘要翻译： 一种方法包括提供具有主表面（17）的单晶硅晶片（11），其支撑掩模层（24），例如二氧化硅或多晶硅，具有窗口（25）以暴露硅晶片的相应区域，形成 碳化硅种子区域（30），例如通过形成碳并将碳转化为碳化硅，以及在碳化硅种子区域上生长单晶碳化硅（31）。 因此，可以在硅晶片上选择性地形成单晶碳化硅，这有助于避免晶片弓形。
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公开(公告)号：US09515222B2
公开(公告)日：2016-12-06
申请号：US14965034
申请日：2015-12-10
发明人： Peter Ward
CPC分类号： H01L33/12 , H01L21/02381 , H01L21/02433 , H01L21/02447 , H01L21/02513 , H01L21/0254 , H01L21/0259 , H01L21/0262 , H01L33/007 , H01L33/0095 , H01L33/32
摘要： We disclose a semiconductor structure comprising a monocrystalline silicon wafer; spaced apart monocrystalline silicon carbide layers disposed directly on the silicon wafer; amorphous and/or polycrystalline silicon carbide layers disposed directly on the silicon wafer between the monocrystalline silicon carbide layers; first gallium nitride layers disposed on the monocrystalline silicon carbide layers; and second gallium nitride layers disposed on the amorphous and/or polycrystalline silicon carbide layers.
摘要翻译： 我们公开了包括单晶硅晶片的半导体结构; 间隔开的单晶碳化硅层直接设置在硅晶片上; 非晶和/或多晶碳化硅层直接设置在单晶碳化硅层之间的硅晶片上; 设置在单晶碳化硅层上的第一氮化镓层; 以及设置在非晶和/或多晶碳化硅层上的第二氮化镓层。
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公开(公告)号：US20140014973A1
公开(公告)日：2014-01-16
申请号：US14034024
申请日：2013-09-23
发明人： Peter WARD
IPC分类号： H01L29/739 , H01L29/66 , H01L29/74
CPC分类号： H01L21/02529 , H01L21/02381 , H01L21/02447 , H01L21/0262 , H01L21/02642 , H01L21/02645 , H01L21/3081 , H01L29/045 , H01L29/1608 , H01L29/66068 , H01L29/66363 , H01L29/7393 , H01L29/7395 , H01L29/74
摘要： A bipolar power semiconductor transistor is disclosed. The transistor includes a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type disposed on the semiconductor substrate; a semiconductor drift region of a second conductivity type, opposite the first conductivity type, disposed on the first semiconductor region, a body region of the first conductivity type located within the semiconductor drift region, a source region of the second conductivity type located within the body region, a gate placed above and in contact to the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region. The semiconductor substrate includes a material having silicon (Si) and the first semiconductor region includes a material having 3-step cubic silicon carbide (3C-SiC).
摘要翻译： 公开了一种双极性功率半导体晶体管。 晶体管包括第一导电类型的半导体衬底，设置在半导体衬底上的第一导电类型的第一半导体区域; 设置在第一半导体区域上的与第一导电类型相反的第二导电类型的半导体漂移区，位于半导体漂移区内的第一导电类型的体区，位于主体内的第二导电类型的源极区 区域，栅极放置在源极区域上方并与源极区域接触的栅极，栅极控制半导体漂移区域和源极区域之间的沟道区域中的电荷，从而控制半导体漂移区域内的电荷流动。 半导体衬底包括具有硅（Si）的材料，并且第一半导体区域包括具有3步立方碳化硅（3C-SiC）的材料。
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公开(公告)号：US20220384181A1
公开(公告)日：2022-12-01
申请号：US17681607
申请日：2022-02-25
摘要： A method is disclosed of manufacturing a semiconductor structure comprising an (001) oriented zincblende structure group III-nitride layer, such as GaN. The layer is formed on a 3C-SiC layer on a silicon substrate. A nucleation layer is formed, recrystallized and then the zincblende structure group III-nitride layer is formed by MOVPE at temperature T3 in the range 750-1000 ° C., to a thickness of at least 0.5μ. There is also disclosed a corresponding semiconductor structure comprising a zincblende structure group III-nitride layer which, when characterized by XRD, shows that the substantial majority, or all, of the layer is formed of zincblende structure group III-nitride in preference to wurtzite structure group III-nitride.
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公开(公告)号：US10157979B2
公开(公告)日：2018-12-18
申请号：US15509517
申请日：2015-09-17
发明人： Peter Ward , Neophytos Lophitis , Tanya Trajkovic , Florin Udrea
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L29/786 , H01L29/861 , H01L29/872 , H01L29/10 , H01L29/16 , H01L29/20 , H01L29/40 , H01L21/266 , H01L27/112 , H01L29/267 , H01L29/36 , H01L29/08 , H01L29/47 , H01L29/739 , H01L29/778 , H01L29/868
摘要： We disclose a high voltage semiconductor device comprising a semiconductor substrate of a second conductivity type; a semiconductor drift region of the second conductivity type disposed over the semiconductor substrate, the semiconductor substrate region having higher doping concentration than the drift region; a semiconductor region of a first conductivity type, opposite to the second conductivity type, formed on the surface of the device and within the semiconductor drift region, the semiconductor region having higher doping concentration than the drift region; and a lateral extension of the first conductivity type extending laterally from the semiconductor region into the drift region, the lateral extension being spaced from a surface of the device.
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公开(公告)号：US11817315B2
公开(公告)日：2023-11-14
申请号：US17681607
申请日：2022-02-25
CPC分类号： H01L21/0254 , H01L21/0262 , H01L21/02381 , H01L21/02447 , H01L21/02458 , H01L29/04 , H01L29/2003 , H01L33/007 , H01L33/32
摘要： A method is disclosed of manufacturing a semiconductor structure comprising an (001) oriented zincblende structure group III-nitride layer, such as GaN. The layer is formed on a 3C-SiC layer on a silicon substrate. A nucleation layer is formed, recrystallized and then the zincblende structure group III-nitride layer is formed by MOVPE at temperature T3 in the range 750-1000° C., to a thickness of at least 0.5μ. There is also disclosed a corresponding semiconductor structure comprising a zincblende structure group III-nitride layer which, when characterized by XRD, shows that the substantial majority, or all, of the layer is formed of zincblende structure group III-nitride in preference to wurtzite structure group III-nitride.
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公开(公告)号：US11302530B2
公开(公告)日：2022-04-12
申请号：US16496388
申请日：2018-03-29
摘要： A method is disclosed of manufacturing a semiconductor structure comprising an (001) oriented zincblende structure group III-nitride layer, such as GaN. The layer is formed on a 3C—SiC layer on a silicon substrate. A nucleation layer is formed, recrystallized and then the zincblende structure group III-nitride layer is formed by MOVPE at temperature T3 in the range 750-1000° C., to a thickness of at least 0.5 μm. There is also disclosed a corresponding semiconductor structure comprising a zincblende structure group III-nitride layer which, when characterized by XRD, shows that the substantial majority, or all, of the layer is formed of zincblende structure group III-nitride in preference to wurtzite structure group III-nitride.
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公开(公告)号：US09082811B2
公开(公告)日：2015-07-14
申请号：US14034024
申请日：2013-09-23
发明人： Peter Ward
CPC分类号： H01L21/02529 , H01L21/02381 , H01L21/02447 , H01L21/0262 , H01L21/02642 , H01L21/02645 , H01L21/3081 , H01L29/045 , H01L29/1608 , H01L29/66068 , H01L29/66363 , H01L29/7393 , H01L29/7395 , H01L29/74
摘要： A bipolar power semiconductor transistor is disclosed. The transistor includes a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type disposed on the semiconductor substrate; a semiconductor drift region of a second conductivity type, opposite the first conductivity type, disposed on the first semiconductor region, a body region of the first conductivity type located within the semiconductor drift region, a source region of the second conductivity type located within the body region, a gate placed above and in contact to the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region. The semiconductor substrate includes a material having silicon (Si) and the first semiconductor region includes a material having 3-step cubic silicon carbide (3C-SiC).
摘要翻译： 公开了一种双极性功率半导体晶体管。 晶体管包括第一导电类型的半导体衬底，设置在半导体衬底上的第一导电类型的第一半导体区域; 设置在第一半导体区域上的与第一导电类型相反的第二导电类型的半导体漂移区，位于半导体漂移区内的第一导电类型的体区，位于主体内的第二导电类型的源极区 区域，栅极放置在源极区域上方并与源极区域接触的栅极，栅极控制半导体漂移区域和源极区域之间的沟道区域中的电荷，从而控制半导体漂移区域内的电荷流动。 半导体衬底包括具有硅（Si）的材料，并且第一半导体区域包括具有3步立方碳化硅（3C-SiC）的材料。
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公开(公告)号：US10714338B2
公开(公告)日：2020-07-14
申请号：US15649733
申请日：2017-07-14
发明人： Peter Ward
IPC分类号： C30B25/18 , H01L21/02 , H01L29/739 , H01L29/16 , H01L29/66 , H01L29/08 , C30B25/02 , C30B29/06 , C30B29/36 , H01L29/34 , H01L29/78 , H01L29/861
摘要： We describe a method for reducing bow in a composite wafer comprising a silicon wafer and a silicon carbide layer grown on the silicon wafer. The method includes applying nitrogen atoms during the growth process of the silicon carbide layer on the silicon wafer so as to generate a compressive stress within the composite wafer.
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